A Modelling Approach To Well-Known And Exotic 2D Materials For Next-Gen FETs


A technical paper titled “Field-Effect Transistors based on 2-D Materials: a Modeling Perspective” was published by researchers at ETH Zurich. Abstract: "Two-dimensional (2D) materials are particularly attractive to build the channel of next-generation field-effect transistors (FETs) with gate lengths below 10-15 nm. Because the 2D technology has not yet reached the same level of maturity... » read more

Analyzing The U.S. Advanced Packaging Ecosystem With Countermeasures To Mitigate HW Security Issues


A technical paper titled “US Microelectronics Packaging Ecosystem: Challenges and Opportunities” was published by researchers at University of Florida, University of Miami, and Skywater Technology Foundry. Abstract: "The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technologica... » read more

Progress In The Fabrication Of CMOS Devices Based On Stacked 2D TMD Nanoribbons (Intel)


A technical paper titled “Process integration and future outlook of 2D transistors” was published by researchers at Intel Corporation. Abstract: "The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the r... » read more

Predicting Defect Properties In Semiconductors With Graph Neural Networks


A technical paper titled “Accelerating Defect Predictions in Semiconductors Using Graph Neural Networks” was published by researchers at Purdue University, Indian Institute of Technology (IIT) Madras, GE Research, and National Institute of Standards and Technology (NIST). Abstract: "Here, we develop a framework for the prediction and screening of native defects and functional impurities i... » read more

Energy Usage in Layers Of Computing (SLAC)


A technical paper titled “Energy Estimates Across Layers of Computing: From Devices to Large-Scale Applications in Machine Learning for Natural Language Processing, Scientific Computing, and Cryptocurrency Mining” was published by researchers at SLAC National Laboratory and Stanford University. Abstract: "Estimates of energy usage in layers of computing from devices to algorithms have bee... » read more

An Overview Of Current Projects In The Open Quantum Hardware Ecosystem With Recommendations 


A technical paper titled “Open Hardware in Quantum Technology” was published by researchers at Unitary Fund, Qruise, Technical University of Valencia, M-Labs Limited, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Laboratories, IQM Quantum Computers, PASQAL, Quantonation, Michigan State University, Università di Camerino, Microsoft Quantum, an... » read more

Patterning With EUV Lithography Without Photoresists


A technical paper titled “Resistless EUV lithography: photon-induced oxide patterning on silicon” was published by researchers at Paul Scherrer Institute, University College London, ETH Zürich, and EPFL. Abstract: "In this work, we show the feasibility of extreme ultraviolet (EUV) patterning on an HF-treated Si(100) surface in the absence of a photoresist. EUV lithography is the leading ... » read more

Fabless Approach To Embed Active Nanophotonics in Bulk CMOS By Co-Designing The BEOL Layers For Optical Functionality (MIT)


A technical paper titled “Metal-Optic Nanophotonic Modulators in Standard CMOS Technology” was published by researchers at Massachusetts Institute of Technology. Abstract: "Integrating nanophotonics with electronics promises revolutionary applications ranging from light detection and ranging (LiDAR) to holographic displays. Although semiconductor manufacturing of nanophotonics in Silicon ... » read more

VCMA-Controlled MTJ Devices For Probabilistic Computing Applications


A technical paper titled “Probabilistic computing with voltage-controlled dynamics in magnetic tunnel junctions” was published by researchers at Northwestern University, University of Messina, Western Digital Corporation, and Universitat Jaume I. Abstract: "Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by convent... » read more

Integration Of Layered Semimetals With Conventional CMOS Platform


A technical paper titled “Layered semimetal electrodes for future heterogeneous electronics” was published by researchers at IIT Madras and Indian Institute of Science Education and Research. Abstract: "Integration of the emerging layered materials with the existing CMOS platform is a promising solution to enhance the performance and functionalities of the future CMOS based integrated cir... » read more

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