A Perovskite-Derivative Nickelate Offering More Durable, Sustainable Multi-Level Non-Volatile Phase Change Memory


A technical paper titled “Thermally Reentrant Crystalline Phase Change in Perovskite-Derivative Nickelate Enabling Reversible Switching of Room-Temperature Electrical Resistivity” was published by researchers at Tohoku University and University of Tsukuba. Abstract: "Reversible switching of room-temperature electrical resistivity due to crystal-amorphous transition is demonstrated in vari... » read more

A Microfluidics Device That Can Perform ANN Computation On Data Stored In DNA


A technical paper titled “Neural network execution using nicked DNA and microfluidics” was published by researchers at University of Minnesota Twin-Cities and Rochester Institute of Technology. Abstract: "DNA has been discussed as a potential medium for data storage. Potentially it could be denser, could consume less energy, and could be more durable than conventional storage media such a... » read more

CXL’s Protection Mechanisms And How They Handle Real-World Security Problems


A technical paper titled “How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel” was published by researchers at University of Cambridge. Abstract: "CXL, a new interconnect standard for cache-coherent memory sharing, is becoming a reality - but its security leaves something to be desired. Decentralized capabilities are flexible and resilient against malicious a... » read more

How A Fault-Tolerant Quantum Memory Could Be Realized Using Near-Term Quantum Processors With Small Qubit Overhead


A technical paper titled “High-threshold and low-overhead fault-tolerant quantum memory” was published by researchers at IBM T.J. Watson Research Center and MIT-IBM Watson AI Lab. Abstract: "Quantum error correction becomes a practical possibility only if the physical error rate is below a threshold value that depends on a particular quantum code, syndrome measurement circuit, and a decod... » read more

An Energy-Efficient 10T SRAM In-Memory Computing Macro Architecture For AI Edge Processor


A technical paper titled “An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor” was published by researchers at Atal Bihari Vajpayee-Indian Institute of Information Technology and Management (ABV-IIITM). Abstract: "In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications.... » read more

Transient Execution Attacks That Leaks Arbitrary Kernel Memory (ETH Zurich)


A technical paper titled “Inception: Exposing New Attack Surfaces with Training in Transient Execution” was published by researchers at ETH Zurich. Abstract: "To protect against transient control-flow hijacks, software relies on a secure state of microarchitectural buffers that are involved in branching decisions. To achieve this secure state, hardware and software mitigations restrict or... » read more

Side-Channel Security Analysis of Intel Optane Persistent Memory


A new technical paper titled "Side-Channel Attacks on Optane Persistent Memory" was published by researchers at University of Virginia, Cornell University, and Graz University of Technology. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "There is a constant evolution of technology for cloud environments, including the development of new memory storage tech... » read more

Modeling and Testing Microarchitectural Leakage of CPU Exceptions (Microsoft, Vrije Universiteit Amsterdam)


A new technical paper titled "Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions" was published by researchers at Microsoft and Vrije Universiteit Amsterdam. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "Microarchitectural leakage models provide effective tools to prevent vulnerabilities such as Spectre and Meltdown vi... » read more

Microarchitectural Side-Channel Attacks And Defenses on NVRAM DIMMs


A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was published by researchers at UC San Diego, Purdue University, and UT Austin. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform r... » read more

Formal Processor Model Providing Provably Secure Speculation For The Constant-Time Policy


A new technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy" was published by researchers at imec-DistriNet, KU Leuven, CEA, and INRIA. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-tim... » read more

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