Information flow policies for NVM Technologies


A new technical paper titled "Automated Information Flow Analysis for Integrated Computing-in-Memory Modules" was published by researchers at RWTH Aachen University. Abstract: "Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (CIM). Various computer architectures... » read more

Data-Centric Reconfigurable Array Chiplets (Princeton)


A technical paper titled "Massive Data-Centric Parallelism in the Chiplet Era" was published by researchers at Princeton University. Abstract: "Traditionally, massively parallel applications are executed on distributed systems, where computing nodes are distant enough that the parallelization schemes must minimize communication and synchronization to achieve scalability. Mapping communica... » read more

CDSAXS Milestones And Future Growth of X-ray-Based Metrology for 3D Nanostructures Important To Chip Industry


A new technical paper titled "Review of the key milestones in the development of critical dimension small angle x-ray scattering at National Institute of Standards and Technology." Abstract: "An x-ray scattering based metrology was conceived over 20 years ago as part of a collaboration between National Institute of Standards and Technology (NIST) and International Business Machines Corporat... » read more

State of the Art And Future Directions of Rowhammer (ETH Zurich)


A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon in... » read more

Spiking Neural Networks: Hardware & Algorithm Developments


A new technical paper titled "Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware" was published by researchers at Purdue University, Pennsylvania State University, and Yale University. Excerpt from Abstract: "In this article, we outline several strides that neuromorphic computing based on spiking neural networks (SNNs) has taken over the recent past, a... » read more

SW-HW Framework: Graphic Rendering on RISC-V GPUs (Georgia Tech, Cal Poly)


A new technical paper titled "Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs" was published by researchers at Georgia Tech, California Polytechnic State University-San Luis Obispo. Abstract Excerpt: "In this work, we present Skybox, a full-stack open-source GPU architecture with integrated software, compiler, hardware, and simulation environment, that enables end-to-end G... » read more

Automated Tool Flow From Domain-Specific Languages To Generate Massively Parallel Accelerators on HBM-Equipped FPGAs


A new technical paper titled "Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics" was published by researchers at Politecnico di Milano and TU Dresden. The paper states "In this article, we propose an automated tool flow from a domain-specific language for tensor expressions to generate massively parallel acceler... » read more

Hybrid Hardware Fuzzer, Combining Capabilities of Formal Verification Methods And Fuzzing Tools


A new technical paper titled "HyPFuzz: Formal-Assisted Processor Fuzzing" was published by researchers at Texas A&M University and Technische Universität Darmstadt. Abstract: "Recent research has shown that hardware fuzzers can effectively detect security vulnerabilities in modern processors. However, existing hardware fuzzers do not fuzz well the hard-to-reach design spaces. Consequently,... » read more

Digital Neuromorphic Processor: Algorithm-HW Co-design (imec / KU Leuven)


A technical paper titled "Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design" was published by researchers at imec and KU Leuven. "In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architect... » read more

Scalable, Shared-L1-Memory Manycore RISC-V System


A new technical paper titled "MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory" was published by researchers at ETH Zurich and University of Bologna. Abstract: "Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly... » read more

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