Shared-Write-Channel-Based Device for High-Density Spin-Orbit-Torque Magnetic Random-Access Memory


ABSTRACT "Spin-orbit-torque (SOT) devices are promising candidates for the future magnetic memory landscape, as they promise high endurance, low read disturbance, and low read error, in comparison with spin-transfer torque devices. However, SOT memories are area intensive due to the requirement for two access transistors per bit. Here, we report a multibit SOT cell that has a single write chan... » read more

Revealing DRAM Operating GuardBands through Workload-Aware Error Predictive Modeling


Abstract Abstract—Improving the energy efficiency of DRAMs becomes very challenging due to the growing demand for storage capacity and failures induced by the manufacturing process. To protect against failures, vendors adopt conservative margins in the refresh period and supply voltage. Previously, it was shown that these margins are too pessimistic and will become impractical due to high ... » read more

Efficient Spin-Orbit Torque Switching with Non-Epitaxial Chalcogenide Heterostructures


Abstract: "The spin–orbit torques (SOTs) generated from topological insulators (TIs) have gained increasing attention in recent years. These TIs, which are typically formed by epitaxially grown chalcogenides, possess extremely high SOT efficiencies and have great potential to be employed in next-generation spintronics devices. However, epitaxy of these chalcogenides is required to ensure the... » read more

A Ferroelectric Semiconductor Field-Effect Transistor


Abstract: "Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are potentially of use in non-volatile memory technology, but they suffer from short retention times, which limits their wider application. Here, we report a ferroelectric sem... » read more

Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study


Abstract "It has become increasingly difficult to understand the complex interaction between modern applications and main memory, composed of DRAM chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, the memory access patterns of prevalent and... » read more

Checkmate: Breaking The Memory Wall With Optimal Tensor Rematerialization


Source: Published on arXiv 10/7/ 2019   Paras Jain Ajay Jain Aniruddha Nrusimha Amir Gholami Pieter Abbeel Kurt Keutzer Ion Stoica Joseph E. Gonzalez A recent paper published on arXiv by a team of UC Berkeley researchers notes that neural networks are increasingly impeded by the limited capacity of on-device GPU memory. The UC Berkeley team uses off-the-shel... » read more

Copy-Row DRAM (CROW) : Substrate for Improving DRAM


Source/Credit: ETH Zurich & Carnegie Mellon University Click here for the technical paper and here for the power point slides » read more

MRAM: from STT to SOT, for security and memory


Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the leading candidates for embedded memory convergence in advanced technology nodes. It is particularly adapted to low-power applications, requiring a decent level of performance. However, it also have interests for secured applications. The PRESENT cipher is a lightweight cryptographic algorithm targeting ultra... » read more

Switching a Perpendicular Ferromagnetic Layer by Competing Spin Currents


ABSTRACT "An ultimate goal of spintronics is to control magnetism via electrical means. One promising way is to utilize a current-induced spin-orbit torque (SOT) originating from the strong spin-orbit coupling in heavy metals and their interfaces to switch a single perpendicularly magnetized ferromagnetic layer at room temperature. However, experimental realization of SOT switching to date req... » read more

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh


Abstract: "The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh ... » read more

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