category: Packaging

category: IoT, Security & Automotive

Optimizing End-to-End Communication And Workload Partitioning In MCM Accelerators (Georgia Tech)
By Technical Paper Link - 03 May, 2025 - Comments: 0

A new technical paper titled "MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules" was published by researchers at Georgia Tech. Abstract "Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher yield, and modular reuse by par... » read more

Inter-Chiplet Interconnect Topologies On Organic And Glass Substrates
By Technical Paper Link - 29 Apr, 2025 - Comments: 0

A new technical paper titled "FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates" was published by researchers at ETH Zurich. Abstract "Chiplet-based systems are rapidly gaining traction in the market. Two packaging options for such systems are the established organic substrates and the emerging glass substrates. These substr... » read more

On-Chiplet Framework for Verifying Physical Security and Integrity of Adjacent Chiplets
By Technical Paper Link - 29 Apr, 2025 - Comments: 0

A new technical paper titled "ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification" was published by researchers at Worcester Polytechnic Institute. Abstract "The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a singl... » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)
By Technical Paper Link - 23 Apr, 2025 - Comments: 0

A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

Board-Level Packaging Method For Device Encapsulation To Enable Water Immersion Cooling
By Technical Paper Link - 14 Apr, 2025 - Comments: 0

A new technical paper titled "Thermally Conductive Electrically Insulating Electronics Packaging for Water Immersion Cooling" was published by researchers at University of Illinois, Urbana, University of Arkansas and UC Berkeley. Abstract "Power densification is making thermal design a key step in the development of future electrical devices. Systems such as data centers and electric vehicl... » read more

Study Of Multi-Die And Multi-Technology Floorplanning (Texas A&M, Duke)
By Technical Paper Link - 05 Apr, 2025 - Comments: 0

A new technical paper titled "PPAC Driven Multi-die and Multi-technology Floorplanning" was published by Texas A&M University and Duke University. Abstract "In heterogeneous integration, where different dies may utilize distinct technologies, floorplanning across multiple dies inherently requires simultaneous technology selection. This work presents the first systematic study of multi-die ... » read more

Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems" was published by researchers at UCLA, Duke University and Arizona State University. Abstract "With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to... » read more

Defect Analysis and Testing Framework For FOWLP Interconnects
By Technical Paper Link - 24 Mar, 2025 - Comments: 0

A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

EFO Errors In The Wire-Bonding Semiconductor Packaging Process
By Technical Paper Link - 19 Mar, 2025 - Comments: 0

A new technical paper titled "A Comparative Study on Various Au Wire Rinse Compositions and Their Effects on the Electronic Flame-Off Errors of Wire-Bonding Semiconductor Package" was published by researchers at Hanbat National University, Seoul National University and Chungnam National University. The paper states: "In this study, we identify the origin of electronic flame-off (EFO) erro... » read more

Multi-Party Computation for Securing Chiplets
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Garblet: Multi-party Computation for Protecting Chiplet-based Systems" was published by Worcester Polytechnic Institute. Abstract "The introduction of shared computation architectures assembled from heterogeneous chiplets introduces new security threats. Due to the shared logical and physical resources, an untrusted chiplet can act maliciously to surreptitiousl... » read more

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