category: Packaging

category: IoT, Security & Automotive

Energy Analysis: 2D and 3D Architectures with Systolic Arrays and CIM (Cornell)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs" was published by researchers at Cornell University. "In this paper, we investigate digital CIM (DCIM) macros and various 3D architectures to find the opportunity of increased energy efficiency compared to 2D structures. Moreover, we also investigated th... » read more

Thermal Modeling For 2.5D And 3D Integrated Chiplets
By Technical Paper Link - 16 Oct, 2024 - Comments: 0

A new technical paper titled "MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures" was published by researchers at University of Wisconsin–Madison, Washington State University, and University of Ulsan. Abstract: "Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D d... » read more

Securing Advanced Packaging Supply Chain With Inherent HW Identifiers Using Imaging Techniques
By Technical Paper Link - 14 Oct, 2024 - Comments: 0

A new technical paper titled "Fault-marking: defect-pattern leveraged inherent fingerprinting of advanced IC package with thermoreflectance imaging" was published by researchers at University of Florida and University of Cincinnati. "This work visits the existing challenges and limitations of traditional embedded fingerprinting and watermarking approaches, and proposes the notion of inherent... » read more

Chiplet-Level HI of Polymer-Based Circuits For Fabricating Flexible Electronic-Photonic Integrated Devices
By Technical Paper Link - 09 Oct, 2024 - Comments: 0

A technical paper titled "Flexible electronic-photonic 3D integration from ultrathin polymer chiplets" was published by researchers at Dartmouth College and Boston University. The paper states: "Here, we present a robust chiplet-level heterogeneous integration of polymer-based circuits (CHIP), where ultrathin polymer electronic and optoelectronic chiplets are vertically bonded at room tempe... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)
By Technical Paper Link - 27 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

Method To Determine The Permittivity of Dielectric Materials in 3D Integrated Structures At Broadband RF Frequencies
By Technical Paper Link - 25 Sep, 2024 - Comments: 0

A new technical paper titled "Characterizing the Broadband RF Permittivity of 3D-Integrated Layers in a Glass Wafer Stack from 100 MHz to 30 GHz" was published by researchers at NIST. Abstract "We present a method for accurately determining the permittivity of dielectric materials in 3D integrated structures at broadband RF frequencies. With applications of microwave and millimeter-wave ele... » read more

SIA’s Report On the State of the U.S. Semiconductor Industry
By Technical Paper Link - 18 Sep, 2024 - Comments: 0

The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report this week, highlighting opportunities for growth, current and emerging challenges, and relevant metrics.  The report reviews the progress made on implementation of the CHIPS Act and associated manufacturing incentives. Supply chain rebalancing, workforce challenges, geopolitics and globa... » read more

3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)
By Technical Paper Link - 12 Sep, 2024 - Comments: 0

A new technical paper titled "TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path" was published by researchers at Pohang University of Science and Technology and Baum Design Systems. Abstract "In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D I... » read more

Scalable Chiplet System for LLM Training, Finetuning and Reduced DRAM Accesses (Tsinghua University)
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A new technical paper titled "Hecaton: Training and Finetuning Large Language Models with Scalable Chiplet Systems" was published by researchers at Tsinghua University. Abstract "Large Language Models (LLMs) have achieved remarkable success in various fields, but their training and finetuning require massive computation and memory, necessitating parallelism which introduces heavy communicat... » read more

ECTC 2024 Session Readout: Advancement of Metrology
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A Electronic Components and Technology Conference (ECTC) session report titled "2024 ECTC Special Session Report: Advancing Metrology for Next-Generation Microelectronics" was published by NIST, Binghamton University, and TechSearch International. Abstract: "Metrology plays a pivotal role in semiconductor research, manufacturing, packaging and assembly. It is critical to the success of this... » read more

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