TFETs: Design and Operation, Including Material Selection and Simulation Methods


A new technical paper titled "Multiscale Simulation and Machine Learning Facilitated Design of Two-Dimensional Nanomaterials-Based Tunnel Field-Effect Transistors: A Review" was published by researchers at University of Chicago and Argonne National Lab. Abstract "Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transi... » read more

Multi-Node, Virtualized Neuromorphic Architecture


A new technical paper titled "NeuroVM: Dynamic Neuromorphic Hardware Virtualization" was published by researchers at Stanford University, UT Austin and Temsa Research & Development Center. Abstract "This paper introduces a novel approach in neuromorphic computing, integrating heterogeneous hardware nodes into a unified, massively parallel architecture. Our system transcends traditional ... » read more

Rowhammer Protection By Addressing Root Cause (Georgia Tech)


A new technical paper titled "Preventing Rowhammer Exploits via Low-Cost Domain-Aware Memory Allocation" was published by researchers at Georgia Tech. Abstract "Rowhammer is a hardware security vulnerability at the heart of every system with modern DRAM-based memory. Despite its discovery a decade ago, comprehensive defenses remain elusive, while the probability of successful attacks grows ... » read more

Review Paper: Challenges Required To Bring the Energy Consumption Down in Microelectronics (Rice, UC Berkeley, Georgia Tech, Et al.)


A new review article titled "Roadmap on low-power electronics" by researchers at Rice University, UC Berkeley, Georgia Tech, TSMC, Intel, Harvard, et al. This roadmap to energy efficient electronics written by numerous collaborators covers materials, modeling, architectures, manufacturing, metrology and more. Find the technical paper here. September 2024. Ramamoorthy Ramesh, Sayeef Sal... » read more

Gold Substrate Plays Boosts Performance of Tellurium-Based Memristors


A new technical paper titled "Non-Volatile Resistive Switching in Nanoscaled Elemental Tellurium by Vapor Transport Deposition on Gold" was published by researchers at Politecnico di Milano, UT Austin, and STMicroelectronics. Abstract: "Two-dimensional (2D) materials are promising for resistive switching in neuromorphic and in-memory computing, as their atomic thickness substantially impr... » read more

Ambipolar Schottky-based FeFET For Ultrascaled Memory Applications


A new technical paper titled "On the Potential of Ambipolar Schottky-Based Ferroelectric Transistor Designs for Enhanced Memory Windows in Scaled Devices" was published by researchers at Global TCAD Solutions, Igor Sikorsky Kyiv Polytechnic Institute, INSA Lyon, and NaMLab. "Here, we promote an ambipolar Schottky-based ferroelectric transistor (AS-FeFET) as an alternative design. We demonstr... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)


A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

Memristors: Flexible Behavioral Model ( Israel Institute of Technology)


A new technical paper titled "VVTEAM: A Compact Behavioral Model for Volatile Memristors" was published by researchers at Technion – Israel Institute of Technology. Abstract "Volatile memristors have recently gained popularity as promising devices for neuromorphic circuits, capable of mimicking the leaky function of neurons and offering advantages over capacitor-based circuits in terms of... » read more

Novel NorthPole Architecture Enables Low-Latency, High-Energy-Efficiency LLM inference (IBM Research)


A new technical paper titled "Breakthrough low-latency, high-energy-efficiency LLM inference performance using NorthPole" was published by researchers at IBM Research. At the IEEE High Performance Extreme Computing (HPEC) Virtual Conference in September 2024, new performance results for their AIU NorthPole AI inference accelerator chip were presented on a 3-billion-parameter Granite LLM. ... » read more

Hardware Acceleration Approach for KAN Via Algorithm-Hardware Co-Design


A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference" was published by researchers at Georgia Tech, TSMC and National Tsing Hua University. Abstract "Recently, a novel model named Kolmogorov-Arnold Networks (KAN) has been proposed with the potential to achieve the functionality of traditional deep neural networks (DNNs) using ... » read more

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