category: Technical Papers

category: IoT, Security & Automotive

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

LLM-based Agentic Framework Automating HW Security Threat Modeling And Test Plan Generation (U. of Florida)
By Technical Paper Link - 01 Apr, 2025 - Comments: 0

A new technical paper titled "ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification" was published by researchers at University of Florida. Abstract "Current hardware security verification processes predominantly rely on manual threat modeling and test plan generation, which are labor-intensive, error-prone, and struggle to scale with increasing ... » read more

Reverse Engineering NVIDIA GPU Cores (Universitat Politècnica de Catalunya)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Analyzing Modern NVIDIA GPU cores" was published by Universitat Politècnica de Catalunya. Abstract "GPUs are the most popular platform for accelerating HPC workloads, such as artificial intelligence and science simulations. However, most microarchitectural research in academia relies on GPU core pipeline designs based on architectures that are more than 15 yea... » read more

Scalable And Energy Efficient Solution for Hardware-Based ANNs (KAUST, NUS)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Synaptic and neural behaviours in a standard silicon transistor" was published by researchers at KAUST and National University of Singapore. Abstract "Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved ... » read more

GPU Analysis Identifying Performance Bottlenecks That Cause Throughput Plateaus In Large-Batch Inference
By Technical Paper Link - 30 Mar, 2025 - Comments: 1

A new technical paper titled "Mind the Memory Gap: Unveiling GPU Bottlenecks in Large-Batch LLM Inference" was published by researchers at Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, and IBM Research. Abstract "Large language models have been widely adopted across different tasks, but their auto-regressive generation nature often leads to inefficient resource util... » read more

Strategies For Reducing The Effective GaN/Diamond TBR
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications" was published by researchers at University of Bristol, Cardiff University and Akash Systems. Abstract "GaN high electron mobility transistors (HEMTs) on SiC substrates are the highest performing commercially available transistors for high-power, hi... » read more

Fully Digital Adaptive PMU-MCU System For Hybrid (Battery-Harvester) IoT Devices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "An Ultra-Low-Leakage Microcontroller with Configurable Power Management for Energy Harvesting IoT Devices" was published by researchers at Eindhoven University of Technology and Innatera Nanosystems. Abstract "This paper presents a power management unit (PMU) architecture designed for energy-harvesting IoT devices, integrating a dual-capacitor system, an ultra-... » read more

HW Implementation Of An ONN Coupled By A ReRAM Crossbar Array (IBM, TU Eindhoven)
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks" was published by researchers at IBM Research Europe and Eindhoven University of Technology. Abstract "We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. ... » read more

Experimental Characterization Results and State-of-the-Art Device-Level Studies of DRAM Read Disturbance
By Technical Paper Link - 25 Mar, 2025 - Comments: 1

A new technical paper titled "Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies" was published by researchers at ETH Zurich. Abstract "Modern DRAM is vulnerable to read disturbance (e.g., RowHammer and RowPress) that significantly undermines the robust operation of the system. Repeatedly opening and closing a DRAM ro... » read more

Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems" was published by researchers at UCLA, Duke University and Arizona State University. Abstract "With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to... » read more

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