category: Power & Performance

category: IoT, Security & Automotive

Mixed Signal In-Memory Computing With Massively Parallel Gradient Calculations of High-Degree Polynomials
By Technical Paper Link - 19 Sep, 2024 - Comments: 0

A new technical paper titled "Computing high-degree polynomial gradients in memory" was published by researchers at UCSB, HP Labs, Forschungszentrum Juelich GmbH, and RWTH Aachen University. Abstract "Specialized function gradient computing hardware could greatly improve the performance of state-of-the-art optimization algorithms. Prior work on such hardware, performed in the context of Isi... » read more

Better Security and Power Efficiency of Ascon HW Implementation with STT-MRAM (CEA, et al.)
By Technical Paper Link - 18 Sep, 2024 - Comments: 0

A new technical paper titled "Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM" was published by researchers at CEA, Leti, Université Grenoble Alpes, CNRS, and Spintec. Abstract "With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards f... » read more

3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)
By Technical Paper Link - 12 Sep, 2024 - Comments: 0

A new technical paper titled "TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path" was published by researchers at Pohang University of Science and Technology and Baum Design Systems. Abstract "In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D I... » read more

Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)
By Technical Paper Link - 10 Sep, 2024 - Comments: 0

A new technical paper titled "Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches" was published by researchers at Graz University of Technology. Abstract "Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation bet... » read more

Analog In-Memory Computing: Fast Deep NN Training (IBM Research)
By Technical Paper Link - 10 Sep, 2024 - Comments: 0

A new technical paper titled "Fast and robust analog in-memory deep neural network training" was published by researchers at IBM Research. Abstract "Analog in-memory computing is a promising future technology for efficiently accelerating deep learning networks. While using in-memory computing to accelerate the inference phase has been studied extensively, accelerating the training phase has... » read more

Fano Resonance in a Si PIC Using a Piezoelectrically Driven Mechanism (Ghent, imec)
By Technical Paper Link - 06 Sep, 2024 - Comments: 0

A new technical paper titled "Piezoelectrically driven Fano resonance in silicon photonics" was published by researchers at Ghent University and imec. Abstract "Piezoelectric optomechanical platforms provide a promising avenue for efficient signal transduction between microwave and optical domains. Lead zirconate titanate (PZT) thin film stands out as a compelling choice for building such... » read more

Microfluidic Cooling Design For Hotspots in Thermal Design Power Chips (Corintis)
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A new technical paper titled "Glacierware: Hotspot-aware Microfluidic Cooling for High TDP Chips using Topology Optimization" was published by researchers at Corintis. Abstract: "The continuous increase in computational power of GPUs, essential for advancements in areas like artificial intelligence and data processing, is driving the adoption of liquid cooling in data centers. Skived copper... » read more

Cooling Technology For Next Gen Power Electronics
By Technical Paper Link - 04 Sep, 2024 - Comments: 0

A new technical paper titled "Advances in Two-Phase Cooling for Next Power Electronics Converters" was published by researchers at ROMA TRE University, ENEA Casaccia Research Center and Sapienza University. "The proposed arrangement allows a greater extraction of the heat at a very low flow rate of the cooling fluid, even with standard industrial-grade heat-sinks, which motivates the use of ... » read more

DL Compiler for Efficiently Utilizing Inter-Core Connected AI Chips (UIUC, Microsoft)
By Technical Paper Link - 28 Aug, 2024 - Comments: 0

A new technical paper titled "Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor" was published by researchers at UIUC and Microsoft Research. Abstract "As AI chips incorporate numerous parallelized cores to scale deep learning (DL) computing, inter-core communication is enabled recently by employing high-bandwidth and low-latency interconnect links on th... » read more

GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency" was published by UC Berkeley. Abstract "Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, limiting the size a... » read more

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