2D UltraLow Temperatures, High Performance Quantum


A new technical paper titled "Electrically tunable giant Nernst effect in two-dimensional van der Waals heterostructures" was published by researchers at EPFL and National Institute for Materials Science (Japan). Abstract "The Nernst effect, a transverse thermoelectric phenomenon, has attracted significant attention for its potential in energy conversion, thermoelectrics and spintronics. ... » read more

Lower Energy, High Performance LLM on FPGA Without Matrix Multiplication


A new technical paper titled "Scalable MatMul-free Language Modeling" was published by UC Santa Cruz, Soochow University, UC Davis, and LuxiTech. Abstract "Matrix multiplication (MatMul) typically dominates the overall computational cost of large language models (LLMs). This cost only grows as LLMs scale to larger embedding dimensions and context lengths. In this work, we show that MatMul... » read more

A Memory Device With MoS2 Channel For High-Density 3D NAND Flash-Based In-Memory Computing


A technical paper titled “Low-Power Charge Trap Flash Memory with MoS2 Channel for High-Density In-Memory Computing" was published by researchers at Kyungpook National University, Sungkyunkwan University, Dankook University, and Kwangwoon University. Abstract: "With the rise of on-device artificial intelligence (AI) technology, the demand for in-memory computing has surged for data-intensiv... » read more

Thermoelectric Active Cooling Hot Spots in Chips


A technical paper titled “Thermoelectric active cooling for transient hot spots in microprocessors” was published by researchers at the University of Pittsburgh and Carnegie Mellon University. Abstract: "Modern microprocessor performance is limited by local hot spots induced at high frequency by busy integrated circuit elements such as the clock generator. Locally embedded thermoelectric ... » read more

ML Method To Predict IR Drop Levels


A new technical paper titled "IR drop Prediction Based on Machine Learning and Pattern Reduction" was published by researchers at National Tsing Hua University, National Taiwan University of Science and Technology, and MediaTek. Abstract (partial) "In this paper, we propose a machine learning-based method to predict IR drop levels and present an algorithm for reducing simulation patterns, w... » read more

Power Electronic Packaging for Discrete Dies


A technical paper titled “Substrate Embedded Power Electronics Packaging for Silicon Carbide MOSFETs” was published by researchers at University of Cambridge, University of Warwick, Chongqing University, and SpaceX. Abstract: "This paper proposes a new power electronic packaging for discrete dies, namely Standard Cell which consists of a step-etched active metal brazed (AMB) substrate and... » read more

KAN: Kolmogorov Arnold Networks: An Alternative To MLPs (MIT, CalTech, et al.)


A new technical paper titled "KAN: Kolmogorov-Arnold Networks" was published by researchers at MIT, CalTech, Northeastern University and The NSF Institute for Artificial Intelligence and Fundamental Interactions. Abstract: "Inspired by the Kolmogorov-Arnold representation theorem, we propose Kolmogorov-Arnold Networks (KANs) as promising alternatives to Multi-Layer Perceptrons (MLPs). While... » read more

Characterizing and Evaluating A Quantum Processor Unit In A HPC Center


A new technical paper titled "Calibration and Performance Evaluation of a Superconducting Quantum Processor in an HPC Center" was published by researchers at Leibniz Supercomputing Centre, IQM Quantum Computers, and Technical University of Munich. Abstract "As quantum computers mature, they migrate from laboratory environments to HPC centers. This movement enables large-scale deployments,... » read more

Device Characteristics of GAA-Structured CMOS and CTFET Under Varying Temperatures


A new technical paper titled "Vertical-Stack Nanowire Structure of MOS Inverter and TFET Inverter in Low-temperature Application" was published by researchers at National Tsing Hua University and National United University in Taiwan. Abstract "Tunneling field effect transistors (TFET) have emerged as promising candidates for integrated circuits beyond conventional metal oxide semiconductor ... » read more

Efficient TNN Inference on RISC-V Processing Cores With Minimal HW Overhead


A new technical paper titled "xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems" was published by researchers at ETH Zurich and Universita di Bologna. Abstract "Ternary neural networks (TNNs) offer a superior accuracy-energy trade-off compared to binary neural networks. However, until now, they have required specialized accelerators to realize their effic... » read more

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