category: Power & Performance

category: IoT, Security & Automotive

Strategies For Reducing The Effective GaN/Diamond TBR
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications" was published by researchers at University of Bristol, Cardiff University and Akash Systems. Abstract "GaN high electron mobility transistors (HEMTs) on SiC substrates are the highest performing commercially available transistors for high-power, hi... » read more

Fully Digital Adaptive PMU-MCU System For Hybrid (Battery-Harvester) IoT Devices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "An Ultra-Low-Leakage Microcontroller with Configurable Power Management for Energy Harvesting IoT Devices" was published by researchers at Eindhoven University of Technology and Innatera Nanosystems. Abstract "This paper presents a power management unit (PMU) architecture designed for energy-harvesting IoT devices, integrating a dual-capacitor system, an ultra-... » read more

Potential of AOS Memories As A High-Performance SRAM Substitute (Georgia Tech, U. of Virginia)
By Technical Paper Link - 21 Mar, 2025 - Comments: 0

A new technical paper titled "Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache" was published by researchers at Georgia Institute of Technology and University of Virginia. Abstract: "The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low oper... » read more

Energy-Efficient Scalable Silicon Photonic Platform For AI Accelerator HW
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators" was published by researchers at HP Labs, IIT Madras, Microsoft Research and University of Michigan. Abstract "The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workload... » read more

Multi-Party Computation for Securing Chiplets
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Garblet: Multi-party Computation for Protecting Chiplet-based Systems" was published by Worcester Polytechnic Institute. Abstract "The introduction of shared computation architectures assembled from heterogeneous chiplets introduces new security threats. Due to the shared logical and physical resources, an untrusted chiplet can act maliciously to surreptitiousl... » read more

A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology. Abstract "3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design f... » read more

Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs" was published by researchers at University of Michigan, Shanghai Jiao Tong University and University of Virginia. Abstract "The rapid advancement of three-dimensional integrated circuits (3DICs) has heightened the need for early-phase design spa... » read more

Thermally Aware Chiplet Placement Algorithm Based on Automatic Differentiation (MIT, IBM)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "DiffChip: Thermally Aware Chip Placement with Automatic Differentiation" was published by researchers at MIT and IBM. Abstract "Chiplets are modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing often leads to significant thermal management challenges, requiring ... » read more

Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)
By Technical Paper Link - 07 Mar, 2025 - Comments: 0

A new technical paper titled "Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies" was published by researcher at the Technical University of Munich (TUM). Abstract "As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field... » read more

Effects Of Reduced Refresh Latency On RowHammer Vulnerability Of DDR4 DRAM Chips
By Technical Paper Link - 04 Mar, 2025 - Comments: 0

A new technical paper titled "Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich, TOBB University of Economics and Technology, and University of Sharjah. Abstract "RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of... » read more

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