category: Power & Performance

category: IoT, Security & Automotive

In-Memory Computing: Techniques for Error Detection and Correction
By Technical Paper Link - 16 Apr, 2024 - Comments: 0

A new technical paper titled "Error Detection and Correction Codes for Safe In-Memory Computations" was published by researchers at Robert Bosch, Forschungszentrum Julich, and Newcastle University. Abstract "In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities... » read more

3-Channel Package-Scale Galvanic Isolation Interface for SiC and GaN Power Switching Converters
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers" was published by STMicroelectronics and DIEEI, Università di Catania. Abstract "This article presents the design of a three-channel package-scale galvanic isolation interface for SiC and GaN power switching converters. The isolation interface consists of two side-by-sid... » read more

2D van der Waals Magnets Above Room Temperature (MIT)
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Field-free deterministic switching of all–van der Waals spin-orbit torque system above room temperature" was published by researchers at MIT, with funding by the NSF and U.S. Department of Energy. Abstract "Two-dimensional van der Waals (vdW) magnetic materials hold promise for the development of high-density, energy-efficient spintronic devices for memory an... » read more

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)
By Technical Paper Link - 02 Apr, 2024 - Comments: 0

A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

High-Temp, High-Electron Mobility MOSFETs Based On N-Type Diamond
By Technical Paper Link - 02 Apr, 2024 - Comments: 0

A new technical paper titled "High-Temperature and High-Electron Mobility Metal-Oxide-Semiconductor Field-Effect Transistors Based on N-Type Diamond" was published by researchers at National Institute for Materials Science (Japan). Abstract: "Diamond holds the highest figure-of-merits among all the known semiconductors for next-generation electronic devices far beyond the performance of c... » read more

New Memory Architecture For Local Differential Privacy in Hardware
By Technical Paper Link - 02 Apr, 2024 - Comments: 0

A technical paper titled "Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory" was published by researchers at North Carolina State University, University of South Alabama, and University of Tennessee. Abstract "The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channe... » read more

Optimizing Event-Based Neural Network Processing For A Neuromorphic Architecture
By Technical Paper Link - 28 Mar, 2024 - Comments: 0

A new technical paper titled "Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration" was published by imec, TU Delft and University of Twente. Abstract "Neuromorphic processors promise low-latency and energy-efficient processing by adopting novel brain-inspired design methodologies. Yet, current neuromorphic solutions still str... » read more

DRAM Cache for GPUs With SCM And High Bandwidth
By Technical Paper Link - 26 Mar, 2024 - Comments: 0

A new technical paper titled "Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory" was published by researchers at POSTECH and Songsil University. Abstract "We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction o... » read more

Designing AI Hardware To Deal With Increasingly Challenging Memory Wall (UC Berkeley)
By Technical Paper Link - 25 Mar, 2024 - Comments: 0

A new technical paper titled "AI and Memory Wall" was published by researchers at UC Berkeley, ICSI, and LBNL. Abstract "The availability of unprecedented unsupervised training data, along with neural scaling laws, has resulted in an unprecedented surge in model size and compute requirements for serving/training LLMs. However, the main performance bottleneck is increasingly shifting to memo... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

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