All-In-One Analog AI Accelerator With CMO/HfOx ReRAM Integrated Into The BEOL (IBM Research-Europe)


A new technical paper titled "All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices" was published by researchers at IBM Research-Europe. Abstract "Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training accelera... » read more

Review Paper: Wafer-Scale Accelerators Versus GPUs (UC Riverside)


A new technical paper titled "Performance, efficiency, and cost analysis of wafer-scale AI accelerators vs. single-chip GPUs" was published by researchers at UC Riverside. "This review compares wafer-scale AI accelerators and single-chip GPUs, examining performance, energy efficiency, and cost in high-performance AI applications. It highlights enabling technologies like TSMC’s chip-on-wafe... » read more

HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)


A new technical paper titled "HBM Roadmap Ver 1.7 Workshop" was published by researchers at KAIST’s TERALAB. The 371-page paper provides an overview of next-generation HBM architectures based on current technology trends, as well as many technology insights. Find the technical paper here or here.  Published June 2025. Advising Professor : Prof. Joungho Kim. Fig. 1: Thermal Manag... » read more

The Impact Of Parameter Uncertainties On The Lifetime Prediction of Power Devices (TU Delft)


A new technical paper titled "Impact of Parameter Uncertainties on Power Electronic Device Lifetime Predictions" was published by researchers at TU Delft. Abstract "Properly addressing uncertainties in reliability analysis is essential for realistic lifetime predictions of power devices. This paper investigates parameter uncertainties on the lifetime estimation of power devices using an emp... » read more

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI)


A new technical paper titled "Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication" was published by researchers at TU Dresden and Centre for Tactile Internet with Human-in-the-Loop (CeTI). Abstract "The evolution of 5G and the emergence of 6G wireless communication systems impose higher demands for computing capabilities and lower power consumption in the... » read more

Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines


A new technical paper titled "Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution" was published by researchers at ETH Zurich, Università di Bologna and Univ. Grenoble Alpes, Inria. Abstract "Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) throu... » read more

Hardware-Oriented Analysis of Multi-Head Latent Attention (MLA) in DeepSeek-V3 (KU Leuven)


A new technical paper titled "Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention" was published by researchers at KU Leuven. Abstract "Multi-Head Latent Attention (MLA), introduced in DeepSeek-V2, improves the efficiency of large language models by projecting query, key, and value tensors into a compact latent space. This architectural change reduces the KV-cache size and s... » read more

Integration of High-Density Polymer Waveguides With Silicon Photonics for CPO (imec, Ghent)


A technical paper titled "Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics" was published by researchers at imec and Ghent University. Abstract "Co-Packaged Optics applications require scalable and high-yield optical interfacing solutions to silicon photonic chiplets, offering low-loss, broadband, and polarization-independent optical coup... » read more

Quantifying The PFAS Impact In ICs Manufacturing (Harvard University)


A new technical paper titled "Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-offs in Energy Efficiency and Environmental Impact of Computing Systems" was published by researchers at Harvard University and Mohamed Bin Zayed University of AI (MBZUAI). "The electronics and semiconductor industry is a prominent consumer of per- and poly-fluoroalkyl substances (PFAS), also known a... » read more

Arithmetic Intensity In Decoding: A Hardware-Efficient Perspective (Princeton University)


A new technical paper titled "Hardware-Efficient Attention for Fast Decoding" was published by researchers at Princeton University. Abstract "LLM decoding is bottlenecked for large batches and long contexts by loading the key-value (KV) cache from high-bandwidth memory, which inflates per-token latency, while the sequential nature of decoding limits parallelism. We analyze the interplay amo... » read more

← Older posts Newer posts →