Enabling Scalable Accelerator Design On Distributed HBM-FPGAs (UCLA)


A technical paper titled “TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs” was published by researchers at University of California Los Angeles. Abstract: "Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale... » read more

Alleviating the DRAM Capacity Bottleneck in Consumer Devices with NVMs


A new technical paper titled "Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD" was published by researchers at ETH Zurich, University of Illinois Urbana-Champaign, Google, and Rivos. Abstract Excerpt "DRAM scalability is becoming a limiting factor to the available memory capacity in... » read more

Diamond Semiconductor: Highest Breakdown Voltage, Lowest Leakage Current


A technical paper titled "Diamond p-Type Lateral Schottky Barrier Diodes With High Breakdown Voltage (4612 V at 0.01 mA/Mm)" was published by researchers at University of Illinois at Urbana–Champaign. Abstract "Diamond p-type lateral Schottky barrier diodes (SBDs) with a 2- μm -thick drift layer are fabricated with and without Al2O3 field plates. Schottky contacts composed of Mo (50 nm) ... » read more

Secure NFC-Based Wireless Battery Management System


A new technical paper titled "Wireless BMS Architecture for Secure Readout in Vehicle and Second life Applications" was published by researchers at TU Graz and NXP. Abstract "Battery management systems (BMS) are becoming increasingly important in the modern age, where clean energy awareness is getting more prominent. They are responsible for controlling large battery packs in modern elect... » read more

A Fast And Unified Toolchain For Rapid Design Space Exploration Of Chiplet Architectures


A technical paper titled “RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet ... » read more

Lateral 3 kV AlN SBDs on Bulk AlN Substrates By MOCVD


A new technical paper titled "3 kV AlN Schottky Barrier Diodes on Bulk AlN Substrates by MOCVD" was published by researchers at Arizona State University. Abstract "This letter reports the first demonstration of AlN Schottky diodes on bulk AlN substrates by metalorganic chemical vapor phase deposition (MOCVD) with breakdown voltages exceeding 3 kV. The devices exhibited good rectifying char... » read more

Investigating Subthreshold Current Suppression in ReS2 Nanosheet-Based FETs


A technical paper titled “Subthreshold Current Suppression in ReS2 Nanosheet-Based Field-Effect Transistors at High Temperatures” was published by researchers at University of Salerno, Università degli studi del Sannio, and University of Exeter. Abstract: "Two-dimensional rhenium disulfide (ReS2), a member of the transition-metal dichalcogenide family, has received significant attention... » read more

Fast Interrupt Extension For MCU RISC-V


A technical paper titled “CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handl... » read more

Continuous Energy Monte Carlo Particle Transport On AI HW Accelerators


A technical paper titled “Efficient Algorithms for Monte Carlo Particle Transport on AI Accelerator Hardware” was published by researchers at Argonne National Laboratory, University of Chicago, and Cerebras Systems. Abstract: "The recent trend toward deep learning has led to the development of a variety of highly innovative AI accelerator architectures. One such architecture, the Cerebras... » read more

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations


A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). Abstract: "Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a ... » read more

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