category: Power & Performance

category: IoT, Security & Automotive

The Vulnerability of Clock Trees to Asymmetric Aging
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations" was published by researchers at Israel Institute of Technology and The Hebrew University of Jerusalem. Abstract "Ensuring integrated circuits (ICs) operate reliably throughout their expected service life is more vital than ever, particularly as they become increasingly central to mis... » read more

STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "System-Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory" was published by researchers at imec, INESC-ID, Université Libre de Bruxelles, et al. "In this paper, we present an system-technology co-optimization (STCO) framework that interfaces with workload-driven system scaling challenges and physical design-enab... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

Critical Design Considerations For High-Bandwidth Chiplet Interconnects (TSMC)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions" was published by researchers at TSMC. Abstract: "The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by Artificial Intelligence a... » read more

Pooling CPU Memory for LLM Inference With Lower Latency and Higher Throughput (UC Berkeley)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "Pie: Pooling CPU Memory for LLM Inference" was published by researchers at UC Berkeley. Abstract "The rapid growth of LLMs has revolutionized natural language processing and AI analysis, but their increasing size and memory demands present significant challenges. A common solution is to spill over to CPU memory; however, traditional GPU-CPU memory swapping ofte... » read more

Backpropagation Algorithm On Neuromorphic Spiking HW (U. Of Zurich, ETH Zurich, LANL)
By Technical Paper Link - 25 Nov, 2024 - Comments: 0

A new technical paper titled "The backpropagation algorithm implemented on spiking neuromorphic hardware" was published by University of Zurich, ETH Zurich, Los Alamos National Laboratory, Royal Institution, London, et al. "This study presents a neuromorphic, spiking backpropagation algorithm based on synfire-gated dynamical information coordination and processing implemented on Intel’s Lo... » read more

Direct-To-Chip Liquid-Cooled Data Centers (Binghamton, Nvidia)
By Technical Paper Link - 22 Nov, 2024 - Comments: 0

A new technical paper titled "Parameters of performance: A deep dive into liquid-to-air CDU assessment" was published by researchers at Binghamton University-SUNY and NVIDIA. Abstract: "The rapid growth in data center workloads and the increasing complexity of modern applications have led to significant contradictions between computational performance and thermal management. Traditional air... » read more

Schottky Barrier Transistors Roadmap (Univ. of Surrey, NaMLab, PGI et al.)
By Technical Paper Link - 17 Nov, 2024 - Comments: 0

A new technical paper titled "Roadmap for Schottky Barrier Transistors" was published by researchers at University of Surrey, NaMLab gGmbH, Forschungszentrum Jülic, Peter Grünberg Institute, et al. Abstract: "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset ... » read more

Ge-Based Multigate SBFETs Operated In An NDR Mode (TU Wien, JKU)
By Technical Paper Link - 15 Nov, 2024 - Comments: 0

A new technical paper titled "Implementation of Negative Differential Resistance-Based Circuits in Multigate Ge Transistors" was published by researchers at TU Wien and JKU (Johannes Kepler University). Abstract: "The co-integration of negative differential resistance (NDR) and Si-based CMOS technology might be a promising concept for multimode devices and circuits with enhanced performance... » read more

Sustainable Hardware Specialization Through Reconfigurable Logic (NUS, Ghent Univ.)
By Technical Paper Link - 15 Nov, 2024 - Comments: 0

A  new technical paper titled "Sustainable Hardware Specialization" was published by researchers at National University of Singapore and Ghent University. "We explore sustainable hardware specialization through reconfigurable logic that has the potential to drastically reduce the environmental footprint compared to a sea of accelerators by amortizing its embodied footprint across multiple a... » read more

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