category: Power & Performance

category: IoT, Security & Automotive

Accelerator Architecture For In-Memory Computation of CNN Inferences Using Racetrack Memory
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems" was published by researchers at National University of Singapore, A*STAR, Chinese Academy of Sciences, and Hong Kong University of Science and Technology. Abstract "Deep neural networks generate and process large volumes of data, posing challe... » read more

Development and Deployment of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel)
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution" was published by researchers at Intel Corporation. Abstract "The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigat... » read more

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich et al.)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A technical paper titled "Data-driven power modeling and monitoring via hardware performance counter tracking" was published by researchers at ETH Zürich, Scuola Superiore Sant’Anna, RISE Research Institutes of Sweden and University of Bologna. Abstract "Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an afforda... » read more

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms" was published by Georgia Tech. Abstract "In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth... » read more

High-Performance p-type 2D FETs By Nitric Oxide Doping (Penn State)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "High-performance p-type bilayer WSe2 field effect transistors by nitric oxide doping" was published by researchers at Penn State University and Florida International University. Abstract "Two-dimensional (2D) materials are promising candidates for next-generation electronics, but the realization of high-performance p-type 2D field-effect transistors (FETs) has... » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)
By Technical Paper Link - 28 Jun, 2025 - Comments: 0

A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Thermoelectricity in Topological Flat-Band Compounds (TU Wien, et al.)
By Technical Paper Link - 18 Jun, 2025 - Comments: 0

A new technical paper titled "Topological Flat-Band-Driven Metallic Thermoelectricity" was published by researchers at TU Wien, Los Alamos National Lab, Flatiron Institute and others. Abstract "Materials where flattened electronic dispersions arise from destructive phase interference, rather than localized orbitals, have emerged as promising platforms for studying emergent quantum phenome... » read more

All-In-One Analog AI Accelerator With CMO/HfOx ReRAM Integrated Into The BEOL (IBM Research-Europe)
By Technical Paper Link - 18 Jun, 2025 - Comments: 0

A new technical paper titled "All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices" was published by researchers at IBM Research-Europe. Abstract "Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training accelera... » read more

Review Paper: Wafer-Scale Accelerators Versus GPUs (UC Riverside)
By Technical Paper Link - 18 Jun, 2025 - Comments: 0

A new technical paper titled "Performance, efficiency, and cost analysis of wafer-scale AI accelerators vs. single-chip GPUs" was published by researchers at UC Riverside. "This review compares wafer-scale AI accelerators and single-chip GPUs, examining performance, energy efficiency, and cost in high-performance AI applications. It highlights enabling technologies like TSMC’s chip-on-wafe... » read more

HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
By Technical Paper Link - 16 Jun, 2025 - Comments: 3

A new technical paper titled "HBM Roadmap Ver 1.7 Workshop" was published by researchers at KAIST’s TERALAB. The 371-page paper provides an overview of next-generation HBM architectures based on current technology trends, as well as many technology insights. Find the technical paper here or here.  Published June 2025. Advising Professor : Prof. Joungho Kim. Fig. 1: Thermal Manag... » read more

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