Designing Heterogeneous AI Acceleration SoCs


A new technical paper titled "Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience" was published by researchers at University of Bologna. Abstract "Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor co... » read more

Recent Advances and Challenges in Processing-in-DRAM (ETH Zurich)


A new technical paper titled "Memory-Centric Computing: Recent Advances in Processing-in-DRAM" was published by researchers at ETH Zurich. Abstract "Memory-centric computing aims to enable computation capability in and near all places where data is generated and stored. As such, it can greatly reduce the large negative performance and energy impact of data access and data movement, by 1) ... » read more

2D Ferroelectric Field-Effect Transistors (Penn State, U. of Minnesota)


A new technical paper titled "Multifunctional 2D FETs exploiting incipient ferroelectricity in freestanding SrTiO3 nanomembranes at sub-ambient temperatures" was published by researchers at Penn State University and University of Minnesota. Abstract "Incipient ferroelectricity bridges traditional dielectrics and true ferroelectrics, enabling advanced electronic and memory devices. Firstly... » read more

In-Depth Study of Low-Power MCUs For Wearables (EPFL)


A new technical paper titled "Enabling Efficient Wearables: An Analysis of Low-Power Microcontrollers for Biomedical Applications" was published by researchers at EPFL. Abstract "Breakthroughs in ultra-low-power chip technology are transforming biomedical wearables, making it possible to monitor patients in real time with devices operating on mere {\mu}W. Although many studies have examined... » read more

Co-Packaged Optics To Train/Run GenAI Models in Data Centers (IBM)


A new technical paper titled "Next generation Co-Packaged Optics Technology to Train & Run Generative AI Models in Data Centers and Other Computing Applications" was published by researchers at IBM. Abstract "We report on the successful design and fabrication of optical modules using a 50 micron pitch polymer waveguide interface, integrated for low loss, high density optical data transf... » read more

CXL’s Potential to Elevate The Capabilities of HPC and AI Applications (Micron, Intel)


A new technical paper titled "Optimizing System Memory Bandwidth with Micron CXL Memory Expansion Modules on Intel Xeon 6 Processors" was published by researchers at Micron and Intel. Abstract "High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads typically demand substantial memory bandwidth and, to a degree, memory capacity. CXL memory expansion modules, also known... » read more

Nonvolatile Electrochemical Memory Cell For Temperatures Up To 600°C (U. Of Michigan, Sandia)


A new technical paper titled "Nonvolatile electrochemical memory at 600°C enabled by composition phase separation" was published by researchers at University of Michigan and Sandia National Laboratories. "Moore’s law has led to monumental advances in computing over the past 50 years. However, one shortcoming of silicon-based logic and memory devices is their limited temperature range, typ... » read more

The Vulnerability of Clock Trees to Asymmetric Aging


A new technical paper titled "The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations" was published by researchers at Israel Institute of Technology and The Hebrew University of Jerusalem. Abstract "Ensuring integrated circuits (ICs) operate reliably throughout their expected service life is more vital than ever, particularly as they become increasingly central to mis... » read more

STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)


A new technical paper titled "System-Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory" was published by researchers at imec, INESC-ID, Université Libre de Bruxelles, et al. "In this paper, we present an system-technology co-optimization (STCO) framework that interfaces with workload-driven system scaling challenges and physical design-enab... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)


A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

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