A HW-Aware Scalable Exact-Attention Execution Mechanism For GPUs (Microsoft)


A technical paper titled “Lean Attention: Hardware-Aware Scalable Attention Mechanism for the Decode-Phase of Transformers” was published by researchers at Microsoft. Abstract: "Transformer-based models have emerged as one of the most widely used architectures for natural language processing, natural language generation, and image generation. The size of the state-of-the-art models has in... » read more

Materials And Technologies For High Temperature, Resilient Electronics


A technical paper titled “Materials for High Temperature Digital Electronics” was published by researchers at University of Pennsylvania, Air Force Research Laboratory, and Ozark Integrated Circuits. Abstract: "Silicon microelectronics, consisting of complementary metal oxide semiconductor (CMOS) technology, have changed nearly all aspects of human life from communication to transportatio... » read more

New Ways To Optimize GEMM-Based Applications Targeting Two Leading AI-Optimized FPGA Architectures


A technical paper titled “Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs” was published by researchers at The University of Texas at Austin and Arizona State University. Abstract: "FPGAs are a promising platform for accelerating Deep Learning (DL) applications, due to their high performance, low power consumption, and reconfigurability. Recently, the leading FPGA... » read more

Thermal Crosstalk Modelling And Compensation Methods for Programmable Photonic ICs (TU Denmark, iPronics)


A technical paper titled “Thermal Crosstalk Modelling and Compensation Methods for Programmable Photonic Integrated Circuits” was published by researchers at the Technical University of Denmark and iPronics Programmable Photonics. Abstract: "Photonic integrated circuits play an important role in the field of optical computing, promising faster and more energy-efficient operations compared... » read more

Optimizing Offload Performance In Heterogeneous Multi-Processor SoCs (ETH Zurich)


A technical paper titled “Optimizing Offload Performance in Heterogeneous MPSoCs” was published by researchers at ETH Zurich. Abstract: "Heterogeneous multi-core architectures combine a few "host" cores, optimized for single-thread performance, with many small energy-efficient "accelerator" cores for data-parallel processing, on a single chip. Offloading a computation to the many-core acc... » read more

Distributing RTL Simulation Across Thousands Of Cores On 4 IPU Sockets (EPFL)


A technical paper titled “Parendi: Thousand-Way Parallel RTL Simulation” was published by researchers at EPFL. Abstract: "Hardware development relies on simulations, particularly cycle-accurate RTL (Register Transfer Level) simulations, which consume significant time. As single-processor performance grows only slowly, conventional, single-threaded RTL simulation is becoming less practical... » read more

Voltage Reference Architectures For Harsh Environments: Quantum Computing And Space


A technical paper titled “Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K” was published by researchers at Delft University of Technology, QuTech, Kavli Institute of Nanoscience Delft, and École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in ... » read more

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)


A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

RF General-Purpose Photonic Processor


A new technical paper titled "General-purpose programmable photonic processor for advanced radiofrequency applications" was published by researchers at Universitat Politècnica de València and iPronics. Abstract "A general-purpose photonic processor can be built integrating a silicon photonic programmable core in a technology stack comprising an electronic monitoring and controlling layer ... » read more

Memristor Crossbar Architecture for Encryption, Decryption and More


A new technical paper titled "Tunable stochastic memristors for energy-efficient encryption and computing" was published by researchers at Seoul National University, Sandia National Laboratories, Texas A&M University and Applied Materials. Abstract "Information security and computing, two critical technological challenges for post-digital computation, pose opposing requirement... » read more

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