category: Power & Performance

category: IoT, Security & Automotive

New Class Of Materials With Increased Band Gap (U. of Minnesota, Caltech)
By Technical Paper Link - 08 Nov, 2024 - Comments: 0

A new technical paper titled "Deep-ultraviolet transparent conducting SrSnO3 via heterostructure design" was published by researchers at University of Minnesota–Twin Cities and Caltech. The researchers "looked at creating a new class of materials with increased “band gap,” enhancing both transparency and conductivity. The new material is a transparent conducting oxide, created with a s... » read more

Two Silicon Switches Driven Both Thermally and Electrically With Ultra-Low-Crosstalk (Cambridge)
By Technical Paper Link - 06 Nov, 2024 - Comments: 0

A new technical paper titled "Ultra-low-crosstalk Silicon Switches Driven Thermally and Electrically" was published by researchers at University of Cambridge and GlitterinTech Limited. Abstract "Silicon photonic switches are widely considered as a cost-effective solution for addressing the ever-growing data traffic in datacenter networks, as they offer unique advantages such as low power co... » read more

Workload-Specific Data Movements Across AI Workloads in Multi-Chiplet AI Accelerators
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "Next-generation artificial intelligence (AI) workloads are posing challenges of scalability and robustness in terms of execution time due to their intrinsic evolving data-intensive characteris... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

Energy Analysis: 2D and 3D Architectures with Systolic Arrays and CIM (Cornell)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs" was published by researchers at Cornell University. "In this paper, we investigate digital CIM (DCIM) macros and various 3D architectures to find the opportunity of increased energy efficiency compared to 2D structures. Moreover, we also investigated th... » read more

Physics-Based Efficient Device Model for Fe-TFTs (Univ. of Florida)
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "An efficient device model for ferroelectric thin-film transistors" was published by researchers at University of Florida. Abstract "Ferroelectric thin-film transistors (Fe-TFTs) have promising potential for flexible electronics, memory, and neuromorphic computing applications. Here, we report on a physics-based efficient device model for Fe-TFTs that effectivel... » read more

3D Device With BEOL-Compatible Channel And Physical Design for Efficient Double-Side Routing
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation, and Carnegie Mellon University. Abstract "This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves ... » read more

GPUs: Bandit Based Framework To Dynamically Reduce Energy Consumption
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "Online Energy Optimization in GPUs: A Multi-Armed Bandit Approach" was published by researchers at Illinois Institute of Technology, Argonne National Lab and Emory University. Abstract "Energy consumption has become a critical design metric and a limiting factor in the development of future computing architectures, from small wearable devices to large-scale lea... » read more

Thermal Modeling For 2.5D And 3D Integrated Chiplets
By Technical Paper Link - 16 Oct, 2024 - Comments: 0

A new technical paper titled "MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures" was published by researchers at University of Wisconsin–Madison, Washington State University, and University of Ulsan. Abstract: "Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D d... » read more

PIO on Current HW Outperforms DMA Over a Range of Payload Sizes In A Number of Different Applications (ETH Zurich)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects" was published by researchers at ETH Zurich. Abstract: "Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers fr... » read more

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