RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks


A new technical paper titled "C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits" was published (preprint) by researchers at University of Southern California. Abstract: "Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have strugg... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration


A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

Mitigating Silent Data Corruptions in High Performance Computing


A new technical paper titled "Mitigating silent data corruptions in HPC applications across multiple program inputs" was published by researchers at University of Iowa, Baidu Security, and Argonne National Lab. The paper was a Best Paper finalist at SC22. The researchers "propose MinpSID, an automated SID framework that automatically identifies and re-prioritizes incubative instructions in a... » read more

Automotive E/E Architectures with Safety Related Availability (SaRa) Requirements For Highly Autonomous Driving


A technical paper titled "Multi-objective optimization for safety-related available E/E architectures scoping highly automated driving vehicles" was written by researchers at Robert Bosch GmBbH and University of Luxembourg. Abstract: "Megatrends such as Highly Automated Driving (HAD) (SAE ≥ Level-3), electrification, and connectivity are reshaping the automotive industry. Together with th... » read more

Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies


A technical paper titled "Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations" was published by researchers at Max Planck Institute for Security and Privacy, Université catholique de Louvain (Belgium), Ruhr University Bochum, and Bundeskriminalamt. "In this work, we aim to improve upon this state of the art by presenting a... » read more

Rowhammer Mitigation: In-DRAM Mechanism Scaling The Number of Refreshes With Activations (ETH Zurich)


A technical paper titled "REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations" was written by researchers at Computer Security Group (COMSEC), ETH Zurich and Zentel Japan. The paper will be presented at IEEE's Symposium on Security and Privacy in May 2023. "With REGA, we propose the first fully in-DRAM mitigation capable of protecting devices independently from their blas... » read more

Hardware Accelerator For Fully Homomorphic Encryption


A technical paper titled "CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data" was published by researchers at MIT, IBM TJ Watson, SRI International, and University of Michigan. "We present CraterLake, the first FHE accelerator that enables FHE programs of unbounded size (i.e., unbounded multiplicative depth). Such computations require very large cipherte... » read more

Hardware Fuzzing (U. of Michigan, Google, Virginia Tech)


A technical paper titled "Fuzzing Hardware Like Software" was published by researchers at University of Michigan, Google and Virginia Tech. The paper was presented at the 2022 Usenix Security Symposium. Abstract: "Hardware flaws are permanent and potent: hardware cannot be patched once fabricated, and any flaws may undermine even formally verified software executing on top. Consequently, ve... » read more

Safeguarding SRAMs From IP Theft (Best Paper Award)


A technical paper titled "Beware of Discarding Used SRAMs: Information is Stored Permanently" was published by researchers at Auburn University. The paper won "Best Paper Award" at the IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) Oct. 25-27 in Huntsville. Abstract: "Data recovery has long been a focus of the electronics industry for decades by s... » read more

Hardware Security: New Mathematical Model To Quantify Information Flow in Digital Circuits For Different Attack Models (RWTH Aachen)


A new technical paper titled "Quantitative Information Flow for Hardware: Advancing the Attack Landscape" was published by researchers at RWTH Aachen University. Abstract: "Security still remains an afterthought in modern Electronic Design Automation (EDA) tools, which solely focus on enhancing performance and reducing the chip size. Typically, the security analysis is conducted by hand, l... » read more

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