category: Security

Better Security and Power Efficiency of Ascon HW Implementation with STT-MRAM (CEA, et al.)

By Technical Paper Link - 18 Sep, 2024 - Comments: 0

A new technical paper titled "Enhancing Security and Power Efficiency of Ascon Hardware Implementation with STT-MRAM" was published by researchers at CEA, Leti, Université Grenoble Alpes, CNRS, and Spintec. Abstract "With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards f... » read more

SIA’s Report On the State of the U.S. Semiconductor Industry

By Technical Paper Link - 18 Sep, 2024 - Comments: 0

The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report this week, highlighting opportunities for growth, current and emerging challenges, and relevant metrics. The report reviews the progress made on implementation of the CHIPS Act and associated manufacturing incentives. Supply chain rebalancing, workforce challenges, geopolitics and globa... » read more

Hardware-Side-Channel Leakage Contracts That Account For Glitches and Transitions (TU Graz)

By Technical Paper Link - 10 Sep, 2024 - Comments: 0

A new technical paper titled "Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches" was published by researchers at Graz University of Technology. Abstract "Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation bet... » read more

Hardware Security: One-Key Premise of Logic Locking

By Technical Paper Link - 30 Aug, 2024 - Comments: 0

A new technical paper titled "Late Breaking Results: On the One-Key Premise of Logic Locking" was published by researchers at Synopsys. Abstract "The evaluation of logic locking methods has long been predicated on an implicit assumption that only the correct key can unveil the true functionality of a protected circuit. Consequently, a locking technique is deemed secure if it resists a good ... » read more

A HW-Based Correct Execution Environment Supporting Virtual Memory (Korea U., KAIST)

By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "A Hardware-Based Correct Execution Environment Supporting Virtual Memory" was published by researchers at Korea University, Korea Advanced Institute of Science and Technology and other universities. Abstract "The rapid increase in data generation has led to outsourcing computation to cloud service providers, allowing clients to handle large tasks without inve... » read more

A Generic Approach For Fuzzing Arbitrary Hypervisors

By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “HYPERPILL: Fuzzing for Hypervisor-bugs by Leveraging the Hardware Virtualization Interface” was presented at the August 2024 USENIX Security Symposium by researchers at EPFL, Boston University, and Zhejiang University. Abstract: "The security guarantees of cloud computing depend on the isolation guarantees of the underlying hypervisors. Prior works have presented... » read more

A Novel Attack For Depleting DNN Model Inference With Runtime Code Fault Injections

By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “Yes, One-Bit-Flip Matters! Universal DNN Model Inference Depletion with Runtime Code Fault Injection” was presented at the August 2024 USENIX Security Symposium by researchers at Peng Cheng Laboratory, Shanghai Jiao Tong University, CSIRO's Data61, University of Western Australia, and University of Waterloo. Abstract: "We propose, FrameFlip, a novel attack ... » read more

Uncovering A Significant Residual Attack Surface For Cross-Privilege Spectre-V2 Attacks

By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “InSpectre Gadget: Inspecting the Residual Attack Surface of Cross-privilege Spectre v2” was presented at the August 2024 USENIX Security Symposium by researchers at Vrije Universiteit Amsterdam. Abstract: "Spectre v2 is one of the most severe transient execution vulnerabilities, as it allows an unprivileged attacker to lure a privileged (e.g., kernel) victim into... » read more

Data Memory-Dependent Prefetchers Pose SW Security Threat By Breaking Cryptographic Implementations

By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “GoFetch: Breaking Constant-Time Cryptographic Implementations Using Data Memory-Dependent Prefetchers” was presented at the August 2024 USENIX Security Symposium by researchers at University of Illinois Urbana-Champaign, University of Texas at Austin, Georgia Institute of Technology, University of California Berkeley, University of Washington, and Carnegie Mellon U... » read more

A New Low-Cost HW-Counterbased RowHammer Mitigation Technique

By Technical Paper Link - 19 Aug, 2024 - Comments: 0

A technical paper titled “ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation” was presented at the August 2024 USENIX Security Symposium by researchers at ETH Zurich. Abstract: "We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening Ro... » read more

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