category: Security

category: IoT, Security & Automotive

HW Security: Flip-Flops Along Logic Gates to Prevent Synthesis Tools’ Structural Leakages (TU Dresden, Ruhr Univ. Bochum)
By Technical Paper Link - 17 Jul, 2024 - Comments: 0

A new technical paper titled "Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks" was published by researchers at TU Dresden and Ruhr University Bochum. Abstract "Machine learning (ML) and algorithmic structural attacks have highlighted the possibility of utilizing structural leakages of an obfuscated circuit to reverse engineer th... » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

Analysis Of The On-DRAM-Die Read Disturbance Mitigation Method: Per Row Activation Counting
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance” was published by researchers at ETH Zürich and TOBB University of Economics and Technology. Abstract: "We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per... » read more

Resilient And Secure Programmable SoC Accelerator Offload (KAUST)
By Technical Paper Link - 03 Jul, 2024 - Comments: 0

A technical paper titled “Resilient and Secure Programmable System-on-Chip Accelerator Offload” was published by researchers at King Abdullah University of Science and Technology (KAUST). Abstract: "Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising plat... » read more

An LLM Approach For Large-Scale SoC Security Verification And Policy Generation (U. of Florida)
By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A technical paper titled “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation” was published by researchers at the University of Florida. Abstract: "Contemporary methods for hardware security verification struggle with adaptability, scalability, and availability due to the increasing complexity of the modern system-on-chips (SoCs). ... » read more

NeuroHammer Attacks on ReRAM-Based Memories
By Technical Paper Link - 21 Jun, 2024 - Comments: 0

A new technical paper titled "NVM-Flip: Non-Volatile-Memory BitFlips on the System Level" was published by researchers at Ruhr-University Bochum, University of Duisburg-Essen, and Robert Bosch. Abstract "Emerging non-volatile memories (NVMs) are promising candidates to substitute conventional memories due to their low access latency, high integration density, and non-volatility. These super... » read more

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)
By Technical Paper Link - 13 Jun, 2024 - Comments: 0

A new technical paper titled "RISC-H: Rowhammer Attacks on RISC-V" was published by researchers at ETH Zurich.  RISC-H will be presented at DRAMSec (co-located with ISCA 2024) Abstract: "The first high-end RISC-V CPU with DDR4 support has been released just a few months ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear whether it is possible to compromise ... » read more

Probing Attacks Against Chiplets
By Technical Paper Link - 11 Jun, 2024 - Comments: 0

A technical paper titled “Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques” was published by researchers at University of Massachusetts and Worcester Polytechnic Institute. Abstract: "Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-... » read more

High Performance and Low-Noise Hardware Board For Side-Channel Evaluations
By Technical Paper Link - 21 May, 2024 - Comments: 0

A new technical paper titled "EFFLUX-F2: A High Performance Hardware Security Evaluation Board" was published by researchers at Nanyang Technological University (Singapore) and Indian Institute of Technology Jodhpur. Abstract "Side-channel analysis has become a cornerstone of modern hardware security evaluation for cryptographic accelerators. Recently, these techniques are also being applie... » read more

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer 
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enh... » read more

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