category: Security

category: IoT, Security & Automotive

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. Abstract "Many verification methods have been proposed to detect microarchitectural information leakage in response to the surge of security breaches in hardware designs. These sophisticated efforts have gone a... » read more

GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores
By Technical Paper Link - 26 Jun, 2025 - Comments: 0

A new technical paper titled "TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs" was published by researchers at University of Connecticut and University of Minnesota. Abstract "hip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being utilized. The use of th... » read more

HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)
By Technical Paper Link - 25 Jun, 2025 - Comments: 0

A new technical paper titled "SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models" was published by researchers at University of Florida. Abstract "Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, c... » read more

Metrics And Methodology for Hardware Security Constructs (NIST)
By Technical Paper Link - 09 Jun, 2025 - Comments: 0

A new technical paper titled "Metrics and Methodology for Hardware Security Constructs" was published by NIST. Abstract "Although hardware is commonly believed to be security-resilient, it is often susceptible to vulnerabilities arising from design and implementation flaws. These flaws have the potential to jeopardize not only the hardware's security, but also its operations and critical us... » read more

V-NAND PUFs (Seoul National University, SK hynix)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A new technical paper titled "Concealable physical unclonable functions using vertical NAND flash memory" was published by researchers at Seoul National University and SK hynix. The paper proposes "a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase." Find the technical paper here. June 2025. Park, SH., Koo, RH., Yang,... » read more

Open-Source And Royalty-Free Confidential Computing For Embedded RISC-V Systems (IBM, Max Planck)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "ACE: Confidential Computing for Embedded RISC-V Systems" was published by researchers at IBM Research, IBM T.J. Watson Research Center, Max Planck Institute for Software Systems (MPI-SWS). Abstract "Confidential computing plays an important role in isolating sensitive applications from the vast amount of untrusted code commonly found in the modern cloud. We a... » read more

Air-Gap Covert Channel Attack On Spread Spectrum Modulated Clocks (IETR, Lab-STICC)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Clock-to-Clock Modulation Covert Channel" was published by researchers at University of Rennes-INSA Rennes-IETR-UMR  and University of South Brittany/Lab-STICC- UMR CNRS. Abstract "Various Electromagnetic (EM) attacks have been developed to modulate and utilize EM emanations for covert communication, including exploiting processors, memory modules, and periphe... » read more

Cache Side-Channel Attacks On LLMs (MITRE, WPI)
By Technical Paper Link - 18 May, 2025 - Comments: 0

A new technical paper titled "Spill The Beans: Exploiting CPU Cache Side-Channels to Leak Tokens from Large Language Models" was published by researchers at MITRE and Worcester Polytechnic Institute. Abstract "Side-channel attacks on shared hardware resources increasingly threaten confidentiality, especially with the rise of Large Language Models (LLMs). In this work, we introduce Spill The... » read more

Cache Occupancy Attacks Targeting The SLC of Apple M-Series SoCs (Northeastern Univ.)
By Technical Paper Link - 11 May, 2025 - Comments: 0

A new technical paper titled "EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks" was published by researchers at Northeastern University. Abstract "Cache occupancy attacks exploit the shared nature of cache hierarchies to infer a victim's activities by monitoring overall cache usage, unlike access-driven cache attacks that focus on spe... » read more

Benefits Of Memory-Centric Computing (ETH Zurich)
By Technical Paper Link - 06 May, 2025 - Comments: 0

A new technical paper titled "Memory-Centric Computing: Solving Computing's Memory Problem" was published by researchers at ETH Zurich. Abstract "Computing has a huge memory problem. The memory system, consisting of multiple technologies at different levels, is responsible for most of the energy consumption, performance bottlenecks, robustness problems, monetary cost, and hardware real esta... » read more

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