98 Hardware Security Failure Scenarios (NIST)


A new technical paper titled "Hardware Security Failure Scenarios: Potential Hardware Weaknesses" was published by NIST. Abstract "Hardware is often assumed to be robust from a security perspective. However, chips are both created with software and contain complex encodings (e.g., circuit designs and firmware). This leads to bugs, some of which compromise security. This publication evaluate... » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)


A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

Effectiveness of Hardware Fuzzing In Detecting Memory Vulnerabilities


A new technical paper titled "Fuzzerfly Effect: Hardware Fuzzing for Memory Safety" was published by researchers at Technical University of Darmstadt, Texas A&M University and Delft University of Technology. Abstract: "Hardware-level memory vulnerabilities severely threaten computing systems. However, hardware patching is inefficient or difficult post-fabrication. We investigate the eff... » read more

Pre-Silicon Verification Method Addressing Critical Aspects of Speculative Execution Vulnerability Detection


A new technical paper titled "Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection" was published by researchers at Technical University of Darmstadt and Texas A&M University. "We introduce Specure, a novel pre-silicon verification method composing hardware fuzzing with Information Flow Tracking (IFT) to address speculative execution leakages. Integrating IFT enables two... » read more

FPGA Fault Injection Attacks (ASU, KIT)


A new technical paper titled "Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics" was published by researchers at Arizona State University and Karlsruhe Institute of Technology (KIT). Abstract "FPGAs are now ubiquitous in cloud computing infrastructures and reconfigurable system-on-chip, particularly for AI acceleration. Major cloud service providers s... » read more

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)


A technical paper titled "A Survey on SoC Security Verification Methods at the Pre-silicon Stage" was recently published by researchers at University of Florida. Abstract "This paper presents a survey of the state-of-the-art pre-silicon security verification techniques for System-on-Chip (SoC) designs, focusing on ensuring that designs, implemented in hardware description languages (HDLs) a... » read more

Distributed Radar Signal Processing Utilizing A Sparse Array To Obfuscate The Data


A new technical paper titled "Signal processing architecture for a trustworthy 77GHz MIMO Radar" was published by researchers at Fraunhofer FHR, Ruhr University Bochum, and Wavesense Dresden GmbH. Abstract "Radar systems are used in safety critical applications in vehicles, so it is necessary to ensure their functioning is reliable and trustworthy. System-on-chip (SoC) radars, which are com... » read more

Securing Advanced Packaging Supply Chain With Inherent HW Identifiers Using Imaging Techniques


A new technical paper titled "Fault-marking: defect-pattern leveraged inherent fingerprinting of advanced IC package with thermoreflectance imaging" was published by researchers at University of Florida and University of Cincinnati. "This work visits the existing challenges and limitations of traditional embedded fingerprinting and watermarking approaches, and proposes the notion of inherent... » read more

Lightweight, High-Performance CPU Extension for Protected Key Handles with CPU-Enforced Usage (CISPA, Ruhr Univ. Bochum)


A new technical paper titled "KeyVisor -- A Lightweight ISA Extension for Protected Key Handles with CPU-enforced Usage Policies" was published by researchers at CISPA Helmholtz Center for Information Security and Ruhr University Bochum. Abstract "The confidentiality of cryptographic keys is essential for the security of protection schemes used for communication, file encryption, and outsou... » read more

Rowhammer Protection By Addressing Root Cause (Georgia Tech)


A new technical paper titled "Preventing Rowhammer Exploits via Low-Cost Domain-Aware Memory Allocation" was published by researchers at Georgia Tech. Abstract "Rowhammer is a hardware security vulnerability at the heart of every system with modern DRAM-based memory. Despite its discovery a decade ago, comprehensive defenses remain elusive, while the probability of successful attacks grows ... » read more

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