On the Design and Misuse of Microcoded (Embedded) Processors — A Cautionary Note


Abstract:  "Today's microprocessors often rely on microcode updates to address issues such as security or functional patches. Unfortunately, microcode update flexibility opens up new attack vectors through malicious microcode alterations. Such attacks share many features with hardware Trojans and have similar devastating consequences for system security. However, due to microcode's opaq... » read more

Usability of Authenticity Checks for Hardware Security Tokens


Abstract:  "The final responsibility to verify whether a newly purchased hardware security token (HST) is authentic and unmodified lies with the end user. However, recently reported attacks on such tokens suggest that users cannot take the security guarantees of their HSTs for granted, even despite widely deployed authenticity checks. We present the first comprehensive market review eva... » read more

Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems


Find Technical Paper link here. Abstract: "Graphics Processing Units (GPUs) are ubiquitous components used across the range of today’s computing platforms, from phones and tablets, through personal computers, to high-end server class platforms. With the increasing importance of graphics and video workloads, recent processors are shipped with GPU devices that are integrated on the same chi... » read more

IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors


Find technical paper link here. Abstract: "To operate efficiently across a wide range of workloads with varying power requirements, a modern processor applies different current management mechanisms, which briefly throttle instruction execution while they adjust voltage and frequency to accommodate for power-hungry instructions (PHIs) in the instruction stream. Doing so 1) reduces the pow... » read more

Hardware-Enabled Security: Container Platform Security Prototype


Date Published: June 2021, NIST Author(s) Michael Bartock (NIST), Murugiah Souppaya (NIST), Jerry Wheeler (Intel), Tim Knoll (Intel), Uttam Shetty (Intel), Ryan Savino (Intel), Joseprabu Inbaraj (AMI), Stefano Righi (AMI), Karen Scarfone (Scarfone Cybersecurity) Abstract In today’s cloud data centers and edge computing, attack surfaces have significantly increased, hacking ha... » read more

Graphene-based PUFs that are reconfigurable and resilient to ML attacks


Researchers at Pennsylvania State University propose using graphene to create physically unclonable functions (PUFs) that are energy efficient, scalable, and secure against AI attacks. Abstract "Graphene has a range of properties that makes it suitable for building devices for the Internet of Things. However, the deployment of such devices will also likely require the development of s... » read more

TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software


"Abstract—Timing side channels have been used to extract cryptographic keys and sensitive documents even from trusted enclaves. Specifically, cache side channels created by reuse of shared code or data in the memory hierarchy have been exploited by several known attacks, e.g., evict+reload for recovering an RSA key and Spectre variants for leaking speculatively loaded data. In this paper, we ... » read more

A Novel PUF Using Stochastic Short-Term Memory Time of Oxide-Based RRAM for Embedded Applications


Abstract: "RRAM suffers from poor retention with short-term memory time when using low compliance current for programing. However, the short-term memory time exhibits ideal randomness, which can be exploited as an entropy source for physically unclonable function (PUF). In this work, we demonstrated a novel PUF utilizing the stochastic short-term memory time of oxide-based RRAM. The proposed P... » read more

Hybrid Boolean Networks as Physically Unclonable Functions


Abstract: "We introduce a Physically Unclonable Function (PUF) based on an ultra-fast chaotic network known as a Hybrid Boolean Network (HBN) implemented on a field programmable gate array. The network, consisting of N coupled asynchronous logic gates displaying dynamics on the sub-nanosecond time scale, acts as a `digital fingerprint' by amplifying small manufacturing variations during a peri... » read more

A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password


Abstract "For the first time, we proposed a 2T complementary architecture of one-time-programmable memory (OTP) in a foundry logic CMOS chip. It was then used to realize the PUF (Physical unclonable function), and the combination with the AI technology to provide a one-time password capability. At first, an OTP was developed based on a novel 2T CMOS unit cell. The experimental results show t... » read more

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