New Memory Architecture For Local Differential Privacy in Hardware


A technical paper titled "Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory" was published by researchers at North Carolina State University, University of South Alabama, and University of Tennessee. Abstract "The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channe... » read more

Verifying Hardware CWEs in RTL Designs Generated by GenAI


A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more

Hardware Trojans: CPU-Oriented Trojan Trigger Circuits (Georgia Tech)


A new technical paper titled "Towards Practical Fabrication Stage Attacks Using Interrupt-Resilient Hardware Trojans" was published by researchers at Georgia Tech. The paper states: "We introduce a new class of hardware trojans called interrupt-resilient trojans (IRTs). Our work is motivated by the observation that hardware trojan attacks on CPUs, even under favorable attack scenarios (e.g.... » read more

U.S. Strategy on Microelectronics Research


The U.S. government released a 61 page report titled "National Strategy on Microelectronics Research" by the Subcommittee On Microelectronics Leadership, Committee on Homeland and National Security of the National Science and Technology Council. The report states four goals guiding the agency's efforts in microelectronics research: "Goal 1. Enable and accelerate research advances for futu... » read more

DRAM Chip Characterization Study of Spatial Variation of Read Disturbance and Future Solutions (ETH Zurich)


A new technical paper titled "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich. Abstract: "Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used for breaking memory isolation, a fundamental building block for building robust systems. Row... » read more

LLMs For EDA, HW Design and Security


A new technical paper titled "Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge" was published by researchers at Kansas State University, University of Science and Technology of China, Michigan Technological University, Washington University in St. Louis and Silicon Assurance. Abstract "In the rapidly evolving semiconductor industry, where research, design... » read more

Suppressing Power Side-Channel Attacks: A HW/SW Design For Resource-Constrained IoT Devices


A technical paper titled “Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices” was published by researchers at Tokyo Institute of Technology and the University of Electro-Communications. Abstract: "With the growth of Internet of Things (IoT) era, the protection of secret information on IoT devices is becoming increasingly important. For IoT devices, atta... » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections


A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

An Analytical EM Model For IC Shielding Against HW Attacks


A technical paper titled “Refined Analytical EM Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework” was published by researchers at Bar-Ilan University and Rafael Defense Systems. Abstract: "Over the past two decades, the prominence of physical attacks on electronic devices, designed to extract confidential information, has surged. These attacks exp... » read more

White-Box Fuzzer With Static Analysis To Detect And Locate Timing Vulnerabilities In RISC-V Processors 


A technical paper titled “WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors” was published by researchers at Indian Institute of Technology Madras, Texas A&M University, and Technische Universität Darmstadt. Abstract: "Timing vulnerabilities in processors have emerged as a potent threat. As processors are the foundation of any computing s... » read more

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