category: Test, Measurement & Analytics

category: IoT, Security & Automotive

A Novel ISO 26262-Compliant Test Bench to Assess the Diagnostic Coverage of Software Hardening Techniques against Digital Components Random Hardware Failures
By Technical Paper Link - 18 Apr, 2022 - Comments: 0

Abstract "This paper describes a novel approach to assess detection mechanisms and their diagnostic coverage, implemented using embedded software, designed to identify random hardware failures affecting digital components. In the literature, many proposals adopting fault injection methods are available, with most of them focusing on transient faults and not considering the functional safety st... » read more

Novel Methods To Enhance Data Quality in FMEA Documents In Semiconductor Manufacturing
By Technical Paper Link - 12 Apr, 2022 - Comments: 0

New research paper from Graz University of Technology & others. Abstract "Digitalization of causal domain knowledge is crucial. Especially since the inclusion of causal domain knowledge in the data analysis processes helps to avoid biased results. To extract such knowledge, the Failure Mode Effect Analysis (FMEA) documents represent a valuable data source. Originally, FMEA documents were de... » read more

Data-driven RRAM device models using Kriging interpolation
By Technical Paper Link - 10 Apr, 2022 - Comments: 0

New technical paper from The George Washington University and NIST with support from DARPA and others. Abstract "A two-tier Kriging interpolation approach is proposed to model jump tables for resistive switches. Originally developed for mining and geostatistics, its locality of the calculation makes this approach particularly powerful for modeling electronic devices with complex behavior la... » read more

NIST Modifies & Improves Technique For Detecting Transistor Defects
By Technical Paper Link - 04 Apr, 2022 - Comments: 0

Abstract "We utilize a frequency-modulated charge pumping methodology to measure quickly and conveniently single “charge per cycle” in highly scaled Si/SiO2 metal–oxide–semiconductor field effect transistors. This is indicative of detection and manipulation of a single interface trap spin species located at the boundary between the SiO2 gate dielectric and Si substrate (almost certainl... » read more

Adaptive NN-Based Root Cause Analysis in Volume Diagnosis for Yield Improvement
By Technical Paper Link - 02 Dec, 2021 - Comments: 1

Abstract "Root Cause Analysis (RCA) is a critical technology for yield improvement in integrated circuit manufacture. Traditional RCA prefers unsupervised algorithms such as Expectation Maximization based on Bayesian models. However, these methods are severely limited by the weak predictive capability of statistical models and can’t effectively transfer the yield learning experience from old... » read more

Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
By Technical Paper Link - 02 Dec, 2021 - Comments: 0

Abstract: "Volume diagnosis and debug play a key role in identifying systematic test failures caused by manufacturing defectivity, design marginalities, and test overkill. However, diagnosis tools often suffer from poor diagnosis resolution. In this paper, we propose techniques to improve diagnosis resolution by test failure clustering and reorganization. The effectiveness of our techniques ... » read more

Data-driven Scheduling for High-mix and Low-volume Production in Semiconductor Assembly and Testing
By Technical Paper Link - 03 Nov, 2021 - Comments: 0

Abstract: The objective of this research is to improve scheduling decisions in high-mix low-volume (HMLV) production environments. Unique characteristics of HMLV semiconductor assembly and testing operations include: (1) Diversified Product Lines: To respond to global competition and different customer needs, manufacturers are providing diversified products to different consumers; (2) Unrelate... » read more

Convolutional Compaction-Based MRAM Fault Diagnosis
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of mult... » read more

MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chi... » read more

Intermittent Undefined State Fault in RRAMs
By Technical Paper Link - 03 Sep, 2021 - Comments: 1

Abstract: " Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes the RRAM device to intermittently c... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy