category: Transistors

category: IoT, Security & Automotive

The Vulnerability of Clock Trees to Asymmetric Aging
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations" was published by researchers at Israel Institute of Technology and The Hebrew University of Jerusalem. Abstract "Ensuring integrated circuits (ICs) operate reliably throughout their expected service life is more vital than ever, particularly as they become increasingly central to mis... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

Schottky Barrier Transistors Roadmap (Univ. of Surrey, NaMLab, PGI et al.)
By Technical Paper Link - 17 Nov, 2024 - Comments: 0

A new technical paper titled "Roadmap for Schottky Barrier Transistors" was published by researchers at University of Surrey, NaMLab gGmbH, Forschungszentrum Jülic, Peter Grünberg Institute, et al. Abstract: "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset ... » read more

Ge-Based Multigate SBFETs Operated In An NDR Mode (TU Wien, JKU)
By Technical Paper Link - 15 Nov, 2024 - Comments: 0

A new technical paper titled "Implementation of Negative Differential Resistance-Based Circuits in Multigate Ge Transistors" was published by researchers at TU Wien and JKU (Johannes Kepler University). Abstract: "The co-integration of negative differential resistance (NDR) and Si-based CMOS technology might be a promising concept for multimode devices and circuits with enhanced performance... » read more

Analysis And Design Of Dual-Layer TFTs (Oregon State Univ., Applied Materials)
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "Dual-Layer Thin-Film Transistor Analysis and Design" was published by researchers at Oregon State University and Applied Materials. Abstract "A set of analytical equations is formulated for the analysis and design of a dual-layer thin-film transistor (TFT). For a given TFT structure, in which each channel layer thickness is specified, drain current is calculate... » read more

High-Temperature Processing of Molybdenum Interconnects
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A technical paper titled "Solving the Annealing of Mo Interconnects for Next-Gen Integrated Circuits" was published by researchers at the National University of Singapore, A*STAR, and imec. Abstract "Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated ... » read more

Improving Power and Speed in GAA-NS FETs
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A new technical paper titled "Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling" was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions. Abstract: "Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around ... » read more

Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)
By Technical Paper Link - 08 Nov, 2024 - Comments: 0

A new technical paper titled "Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM" was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ). Abstract "Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Sco... » read more

Characterizing Defects Inside Hexagonal Boron Nitride (KAIST, NYU, et al.)
By Technical Paper Link - 23 Oct, 2024 - Comments: 0

A new technical paper titled "Characterizing Defects Inside Hexagonal Boron Nitride Using Random Telegraph Signals in van der Waals 2D Transistors" was published by researchers at KAIST, NYU, Brookhaven National Laboratory, and National Institute for Materials Science. Abstract: "Single-crystal hexagonal boron nitride (hBN) is used extensively in many two-dimensional electronic and quantu... » read more

Scalability of Nanosheet Oxide FETs for Monolithic 3-D Integration
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling" was published by researchers at The University of Tokyo and Nara Institute of Science and Technology. Abstract "We have investigated the scaling potential of nanosheet oxide semiconductor FETs (NS OS FETs) for monolithic 3-D (M3D) integration in t... » read more

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