category: Transistors

category: IoT, Security & Automotive

Potential of AOS Memories As A High-Performance SRAM Substitute (Georgia Tech, U. of Virginia)
By Technical Paper Link - 21 Mar, 2025 - Comments: 0

A new technical paper titled "Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache" was published by researchers at Georgia Institute of Technology and University of Virginia. Abstract: "The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low oper... » read more

Design Optimization Techniques To Improve NC-CFET Performance
By Technical Paper Link - 14 Mar, 2025 - Comments: 0

A new technical paper titled "Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configu... » read more

Review Of Recent Advancements in THz-based 6G: Devices, Circuits, Antennas and Packaging
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "A Survey on Advancements in THz Technology for 6G: Systems, Circuits, Antennas, and Experiments" was published by UCLA. Abstract "Terahertz (THz) carrier frequencies (100 GHz to 10 THz) have been touted as a source for unprecedented wireless connectivity and high-precision sensing, courtesy of their wide bandwidth availability and small wavelengths. However, no... » read more

Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs" was published by researchers at University of Michigan, Shanghai Jiao Tong University and University of Virginia. Abstract "The rapid advancement of three-dimensional integrated circuits (3DICs) has heightened the need for early-phase design spa... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

Low-Temp Pressure-Assisted Liquid-Metal Printing for Oxide-TFTs
By Technical Paper Link - 25 Feb, 2025 - Comments: 0

A new technical paper titled "Low-temperature pressure-assisted liquid-metal printing for β-Ga2O3 thin-film transistors" was published by researchers at UCSD and National Tsing Hua University. Abstract "Developing a low-temperature and cost-effective manufacturing process for energy-efficient and high-performance oxide-thin-film transistors (TFTs) is a crucial step toward advanci... » read more

Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

CFETs with Optimized Buried Power Rails
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A technical paper titled "Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)" was published by researchers at Korea University and Sungkyunkwan University. Abstract "In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technolog... » read more

Demonstration Of An ALD IWO Channel In A GAA Nanosheet FET Structure (Georgia Tech, Micron)
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "First Demonstration of High-Performance and Extremely Stable W-Doped In2O3  Gate-All-Around (GAA) Nanosheet FET" was published by researchers at Georgia Institute of Technology and Micron. Abstract "We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In2O3), or indium tungsten oxide ... » read more

Simulation Study Of Vertically Stacked 2D NSFETs
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more

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