category: Transistors

category: IoT, Security & Automotive

Transistor Sizing Approach for OTA Circuits Using a Transformer Architecture
By Technical Paper Link - 07 Feb, 2025 - Comments: 0

A  new technical paper titled "Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables" was published by University Minnesota and Cadence. Abstract: "Device sizing is crucial for meeting performance specifications in operational transconductance amplifiers (OTAs), and this work proposes an automated sizing framework based on a transform... » read more

Indium Tungsten Oxide (IWO) Thin-Film Transistors
By Technical Paper Link - 04 Feb, 2025 - Comments: 0

A new technical paper titled "Thermally Dependent Metastability of Indium-Tungsten-Oxide Thin-Film Transistors" was published by researchers at Rochester Institute of Technology and Corning Research and Development Corporation. Abstract "Indium tungsten oxide (IWO) has been investigated as an oxide semiconductor candidate for next-generation thin-film transistors (TFTs). Bottom-gate TFTs we... » read more

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)
By Technical Paper Link - 24 Jan, 2025 - Comments: 0

A new technical paper titled "SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology" was published by researchers at IBM T. J. Watson Research Center and IBM. Abstract "A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros ... » read more

Electronic and Transport Properties of Six TMD Heterostructures
By Technical Paper Link - 24 Jan, 2025 - Comments: 0

A new technical paper titled "Computational Assessment of I–V Curves and Tunability of 2D Semiconductor van der Waals Heterostructures" was published by researchers at Chalmers University of Technology. Abstract "Two-dimensional (2D) transition metal dichalcogenides (TMDs) have received significant interest for use in tunnel field-effect transistors (TFETs) due to their ultrathin layers... » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)
By Technical Paper Link - 17 Jan, 2025 - Comments: 0

A new technical paper titled "Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories" was published by researchers at Georgia Tech and UCLA. Abstract "This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power ef... » read more

Schottky Barrier Transistors: Status, Challenges and Modeling Tools
By Technical Paper Link - 08 Jan, 2025 - Comments: 0

A technical paper titled "Roadmap for Schottky barrier transistors" was published by researchers at University of Surrey, Namlab gGmbH, Forschungszentrum Jülich (FZJ), et al. Abstract "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functio... » read more

The Vulnerability of Clock Trees to Asymmetric Aging
By Technical Paper Link - 03 Dec, 2024 - Comments: 0

A new technical paper titled "The Impact of Asymmetric Transistor Aging on Clock Tree Design Considerations" was published by researchers at Israel Institute of Technology and The Hebrew University of Jerusalem. Abstract "Ensuring integrated circuits (ICs) operate reliably throughout their expected service life is more vital than ever, particularly as they become increasingly central to mis... » read more

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

Schottky Barrier Transistors Roadmap (Univ. of Surrey, NaMLab, PGI et al.)
By Technical Paper Link - 17 Nov, 2024 - Comments: 0

A new technical paper titled "Roadmap for Schottky Barrier Transistors" was published by researchers at University of Surrey, NaMLab gGmbH, Forschungszentrum Jülic, Peter Grünberg Institute, et al. Abstract: "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset ... » read more

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