Ge-Based Multigate SBFETs Operated In An NDR Mode (TU Wien, JKU)


A new technical paper titled "Implementation of Negative Differential Resistance-Based Circuits in Multigate Ge Transistors" was published by researchers at TU Wien and JKU (Johannes Kepler University). Abstract: "The co-integration of negative differential resistance (NDR) and Si-based CMOS technology might be a promising concept for multimode devices and circuits with enhanced performance... » read more

Analysis And Design Of Dual-Layer TFTs (Oregon State Univ., Applied Materials)


A new technical paper titled "Dual-Layer Thin-Film Transistor Analysis and Design" was published by researchers at Oregon State University and Applied Materials. Abstract "A set of analytical equations is formulated for the analysis and design of a dual-layer thin-film transistor (TFT). For a given TFT structure, in which each channel layer thickness is specified, drain current is calculate... » read more

High-Temperature Processing of Molybdenum Interconnects


A technical paper titled "Solving the Annealing of Mo Interconnects for Next-Gen Integrated Circuits" was published by researchers at the National University of Singapore, A*STAR, and imec. Abstract "Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated ... » read more

Improving Power and Speed in GAA-NS FETs


A new technical paper titled "Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling" was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions. Abstract: "Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around ... » read more

Non-Stateful Logic Gates in ReRAM (RWTH Aachen, FZJ)


A new technical paper titled "Experimental Verification and Evaluation of Non-Stateful Logic Gates in Resistive RAM" was published by researchers at RWTH Aachen University and Forschungszentrum Jülich GmbH (FZJ). Abstract "Resistively switching, non-volatile memory devices facilitate new logic paradigms by combining storage and processing elements. Several non-stateful concepts such as Sco... » read more

Characterizing Defects Inside Hexagonal Boron Nitride (KAIST, NYU, et al.)


A new technical paper titled "Characterizing Defects Inside Hexagonal Boron Nitride Using Random Telegraph Signals in van der Waals 2D Transistors" was published by researchers at KAIST, NYU, Brookhaven National Laboratory, and National Institute for Materials Science. Abstract: "Single-crystal hexagonal boron nitride (hBN) is used extensively in many two-dimensional electronic and quantu... » read more

Scalability of Nanosheet Oxide FETs for Monolithic 3-D Integration


A new technical paper titled "High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling" was published by researchers at The University of Tokyo and Nara Institute of Science and Technology. Abstract "We have investigated the scaling potential of nanosheet oxide semiconductor FETs (NS OS FETs) for monolithic 3-D (M3D) integration in t... » read more

Physics-Based Efficient Device Model for Fe-TFTs (Univ. of Florida)


A new technical paper titled "An efficient device model for ferroelectric thin-film transistors" was published by researchers at University of Florida. Abstract "Ferroelectric thin-film transistors (Fe-TFTs) have promising potential for flexible electronics, memory, and neuromorphic computing applications. Here, we report on a physics-based efficient device model for Fe-TFTs that effectivel... » read more

3D Device With BEOL-Compatible Channel And Physical Design for Efficient Double-Side Routing


A new technical paper titled "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation, and Carnegie Mellon University. Abstract "This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves ... » read more

Strain Engineering in 2D FETs (UCSB)


A new technical paper titled "Strain engineering in 2D FETs: Physics, status, and prospects" was published by researchers at UC Santa Barbara. "In this work, we explore the physics and evaluate the merits of strain engineering in two-dimensional van der Waals semiconductor-based FETs (field-effect-transistors) using DFT (density functional theory) to determine the modulation of the channel m... » read more

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