category: Transistors

category: IoT, Security & Automotive

Physics-Based Efficient Device Model for Fe-TFTs (Univ. of Florida)
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "An efficient device model for ferroelectric thin-film transistors" was published by researchers at University of Florida. Abstract "Ferroelectric thin-film transistors (Fe-TFTs) have promising potential for flexible electronics, memory, and neuromorphic computing applications. Here, we report on a physics-based efficient device model for Fe-TFTs that effectivel... » read more

3D Device With BEOL-Compatible Channel And Physical Design for Efficient Double-Side Routing
By Technical Paper Link - 17 Oct, 2024 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation, and Carnegie Mellon University. Abstract "This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves ... » read more

Strain Engineering in 2D FETs (UCSB)
By Technical Paper Link - 07 Oct, 2024 - Comments: 0

A new technical paper titled "Strain engineering in 2D FETs: Physics, status, and prospects" was published by researchers at UC Santa Barbara. "In this work, we explore the physics and evaluate the merits of strain engineering in two-dimensional van der Waals semiconductor-based FETs (field-effect-transistors) using DFT (density functional theory) to determine the modulation of the channel m... » read more

TFETs: Design and Operation, Including Material Selection and Simulation Methods
By Technical Paper Link - 07 Oct, 2024 - Comments: 0

A new technical paper titled "Multiscale Simulation and Machine Learning Facilitated Design of Two-Dimensional Nanomaterials-Based Tunnel Field-Effect Transistors: A Review" was published by researchers at University of Chicago and Argonne National Lab. Abstract "Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transi... » read more

Review Paper: Challenges Required To Bring the Energy Consumption Down in Microelectronics (Rice, UC Berkeley, Georgia Tech, Et al.)
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new review article titled "Roadmap on low-power electronics" by researchers at Rice University, UC Berkeley, Georgia Tech, TSMC, Intel, Harvard, et al. This roadmap to energy efficient electronics written by numerous collaborators covers materials, modeling, architectures, manufacturing, metrology and more. Find the technical paper here. September 2024. Ramamoorthy Ramesh, Sayeef Sal... » read more

Ambipolar Schottky-based FeFET For Ultrascaled Memory Applications
By Technical Paper Link - 06 Oct, 2024 - Comments: 0

A new technical paper titled "On the Potential of Ambipolar Schottky-Based Ferroelectric Transistor Designs for Enhanced Memory Windows in Scaled Devices" was published by researchers at Global TCAD Solutions, Igor Sikorsky Kyiv Polytechnic Institute, INSA Lyon, and NaMLab. "Here, we promote an ambipolar Schottky-based ferroelectric transistor (AS-FeFET) as an alternative design. We demonstr... » read more

Flexible IGZO RISC-V Microprocessor
By Technical Paper Link - 26 Sep, 2024 - Comments: 0

A new technical paper titled "Bendable non-silicon RISC-V microprocessor" was published by researchers at Pragmatic Semiconductor, Qamcom,  and Harvard University. From the abstract: "Here we present Flex-RV, a 32-bit microprocessor based on an open RISC-V instruction set fabricated with indium gallium zinc oxide thin-film transistors on a flexible polyimide substrate, enabling an ultralow... » read more

Dualtronics: Photonic Devices on the Cation Face and Electronic Devices on the Anion Face of the Same Wafer
By Technical Paper Link - 26 Sep, 2024 - Comments: 0

A new technical paper titled "Using both faces of polar semiconductor wafers for functional devices" was published by researchers at Cornell University and Polish Academy of Sciences. Find the technical paper here. Published September 2024. Cornell University's news release is here, stating "Cornell researchers, in collaboration with a team at the Polish Academy of Sciences, have develope... » read more

Models for Both Strained and Unstrained GAA FETs Using Neural Networks
By Technical Paper Link - 23 Sep, 2024 - Comments: 0

A new technical paper titled "Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach" was published by researchers at Hanyang University and Alsemy Inc. Abstract "Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D... » read more

Improving The Air-Stability and NBTI Reliability of BEOL CNFETs
By Technical Paper Link - 19 Sep, 2024 - Comments: 0

A new technical paper titled "Overcoming Ambient Drift and Negative-Bias Temperature Instability in Foundry Carbon Nanotube Transistors" was published by researchers at MIT, Stanford University, Carnegie Mellon University and Analog Devices. Abstract: "Back-end-of-line (BEOL) logic integration is emerging as a complementary scaling path to supplement front-end-of-line (FEOL) Silicon. Among ... » read more

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