IP/SoC Verification With Assertions


There's been a lot of excitement here in Silicon Valley these past weeks with the opening of the new 49ers stadium. I've always found it amazing to see how so many complex, fundamentally different technologies — mechanical, electrical, HVAC, plumbing, audiovisual, food catering, etc. — can be put together to create a functioning ballpark. It all but takes a mastermind to bring all these eng... » read more

Constraints Ubiquity: Impact On Managing Design Closure?


By Mark Baker and Ravindra Aneja Maintaining completeness, correctness and consistency of design constraints is a challenge that is pervasive in the design flow. Multiple transformations, or touch points (as illustrated in the diagram below), exist during the design implementation stages. Additionally, there are parallel stages involving IP development and handoff resulting in SoC integration ... » read more

Does EDA Consider RTL Power Optimization As Job Done?


The “Power Buzz” leading into this year’s Design Automation Conference was around System Level Power Architecture and Optimization—some would say the natural progression of EDA towards the next big customer design challenge. This does beg the question of whether EDA considers RTL Power Optimization a mature solution. All products or solutions progress through various stages of maturity,... » read more

Productive Clock Domain Crossing Verification


Recently, we were invited to participate in an internal [email protected] event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

Can RTL Power Estimation Accuracy Be Improved?


The power targets for today’s complex SoC designs force design teams to address power optimization earlier and more effectively than ever before. In recent years, design teams have migrated to RTL power estimation solutions to identify areas of potential power savings to be used in early design tradeoffs. RTL power estimation accuracy at 15% to 20% to gate-level power numbers is deemed accept... » read more

UPF-Friendly RTL


On a recent customer visit, we were introduced to a new term – new to us at least – “UPF-friendly RTL”. While I hadn’t heard the term, I have been going on about the concept for some time – to the point, no doubt, of becoming terminally boring. We’ve had several customers quietly doing this for years, but now I’m starting to hear it from more customers, and from 1801 committee m... » read more

Power Verification in Sochi?


An estimated 3 billion viewers watched in wonder at the high tech artistry of the opening ceremonies of the $50 billion Sochi Winter Olympics. As many viewers later learned, these events are often not without glitches. The after buzz was all about the Olympic ring failure. When only four of the five snowflakes transitioned into rings, the broadcasters resorted to rehearsal footage attempting to... » read more

Power Resolutions For 2014


As the ball dropped at midnight in New York’s Time Square, signifying the beginning of 2014, many had already decided on their resolutions for the New Year. Others decide during the first few days of the New Year. Undoubtedly, consideration involves common resolutions that we fall back on year after year. Individuals might think about health, losing weight and becoming more fit. Others think ... » read more

Door Busters In Low Power Optimization


The holiday season is upon us, notably a shortened gift buying season at that, which for some only adds to the anxiety felt at this time of year. Many shoppers are out there searching for a door buster deal on that “hot item,” but choices must be made on where to allocate one’s time. Should one stop with the door buster deals or take the time to look further for more practical or traditio... » read more

What Do Timing Constraints Have To Do With Clock Domain Crossing?


As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality timing constraints not only reduce the total effort required to achieve timing closure, but also reduce the number of iterations during that process. In the worst case, incorrect timing constraints ca... » read more

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