EDA’s Role Grows For Preventing And Identifying Failures


The front end of design is becoming more tightly integrated with the back end of manufacturing, driven by the rising cost and impact of failures in advanced chips and critical applications. Ironically, the starting point for this shift is failure analysis (FA), which typically happens when a device fails to yield, or worse, when it is returned due to some problem. In production, that leads t... » read more

Startup Funding: May 2023


Photonic interconnects were an area of activity in May, with two companies raising funds for what could be much faster chip-to-chip and chiplet-to-chiplet links. Microstructured optics and metasurfaces also drew investment, with four companies creating products for a range of applications from flexible LEDs to multi-wavelength spectral imaging. The large language models that power many gener... » read more

Holistic Power Reduction


The power consumption of a device is influenced by every stage of the design, development, and implementation process, but identifying opportunities to save power no longer can be just about making hardware more efficient. Tools and methodologies are in place for most of the power-saving opportunities, from RTL down through implementation, and portions of the semiconductor industry already a... » read more

Making Tradeoffs With AI/ML/DL


Machine learning, deep learning, and AI increasingly are being used in chip design, and they are being used to design chips that are optimized for ML/DL/AI. The challenge is understanding the tradeoffs on both sides, both of which are becoming increasingly complex and intertwined. On the design side, machine learning has been viewed as just another tool in the design team's toolbox. That's s... » read more

Rethinking Engineering Education In The U.S.


The CHIPS Act, as well as the ongoing need for talent, is causing both industry and academia in America to rethink engineering education, resulting in new approaches and stronger partnerships. As an example, Arizona State University (ASU) now has a Secure, Trusted, and Assured Microelectronics Center (STAM). The center offers an interdisciplinary approach to learning secure and trusted semic... » read more

Designing Crash-Proof Autonomous Vehicles


Autonomous vehicles keep crashing into things, even though ADAS technology promises to make driving safer because machines can think and react faster than human drivers. Humans rely on seeing and hearing to assess driving conditions. When drivers detect objects in front of the vehicle, the automatic reaction is to slam on the brakes or swerve to avoid them. Quite often drivers cannot react q... » read more

Thermal Integrity Challenges Grow In 2.5D


Thermal integrity is becoming much harder to predict accurately in 2.5D and 3D-IC, creating a cascade of issues that can affect everything from how a system behaves to reliability in the field. Over the past decade, silicon interposer technology has evolved from a simple interconnect into a critical enabler for heterogeneous integration. Interposers today may contain tens of dies or chiplets... » read more

What Designers Need To Know About GAA


While only 12 years old, finFETs are reaching the end of the line. They are being supplanted by gate-all-around (GAA), starting at 3nm [1], which is expected to have a significant impact on how chips are designed. GAAs come in two main flavors today — nanosheets and nanowires. There is much confusion about nanosheets, and the difference between nanosheets and nanowires. The industry still ... » read more

Transitioning To Photonics


Silicon photonics is undergoing a resurgence as traditional approaches for reducing power and heat become more difficult and expensive, opening the door to a whole new set of technological challenges and driving up demand for a skill set that is in short supply today. From a technology standpoint, photonics is extremely complex. Signals drift, they are modulated with heat, and structures lik... » read more

RISC-V Driving New Verification Concepts


Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

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