Improving Energy And Power Efficiency In The Data Center


Energy costs in data centers are soaring as the amount of data being generated explodes, and it's being made worse by an imbalance between increasingly dense processing elements that are producing more heat and uneven server utilization, which requires more machines to be powered up and cooled. The challenge is to maximize utilization without sacrificing performance, and in the past that has... » read more

What Is An xPU?


Almost every day there is an announcement about a new processor architecture, and it is given a three-letter acronym — TPU, IPU, NPU. But what really distinguishes them? Are there really that many unique processor architectures, or is something else happening? In 2018, John L. Hennessy and David A. Patterson delivered the Turing lecture entitled, "A New Golden Age for Computer Architecture... » read more

Improving Power Efficiency In Ultra-Low Power Designs


Faster data communications in phones and data centers grabs headlines, but many applications don't require the continuous, high-data-rate communications needed for video streaming or image processing. In fact, for many devices, designing for better performance results in wasted energy and sharply curtails the time between battery charges. That is especially true for machine-to-machine (M2M) ... » read more

Changing Server Architectures In The Data Center


Data centers are undergoing a fundamental shift to boost server utilization and improve efficiency, optimizing architectures so available compute resources can be leveraged wherever they are needed. Traditionally, data centers were built with racks of servers, each server providing computing, memory, interconnect, and possibly acceleration resources. But when a server is selected, some of th... » read more

Get Ready For The Next Generation Of Wearable Tech


Wearables have attracted a lot of attention recently, due to both their successes as well as failures. They bring together requirements for packaging, new substrates, power scavenging, low-power, novel connectivity, flexibility, durability, as well as fashion. While some of the challenges remain formidable, the long-term potential is driving the industry to look at what is possible. They are... » read more

HBM3: Big Impact On Chip Design


An insatiable demand for bandwidth in everything from high-performance computing to AI training, gaming, and automotive applications is fueling the development of the next generation of high-bandwidth memory. HBM3 will bring a 2X bump in bandwidth and capacity per stack, as well as some other benefits. What was once considered a "slow and wide" memory technology to reduce signal traffic dela... » read more

Architecting Interposers


An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

Will Co-Packaged Optics Replace Pluggables?


As optical connections work their way deeper into the data center, a debate is underway. Is it better to use pluggable optical modules or to embed lasers deep into advanced packages? There are issues of convenience, power, and reliability driving the discussion, and an eventual winner isn’t clear yet. “The industry is definitely embracing co-packaged optics,” said James Pond, principal... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects


Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

Wrestling With Analog At 3nm


Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry. As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process te... » read more

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