category: Top Stories

category: IoT, Security & Automotive

Upcoming Challenges And Changes In Semiconductor Materials
By Laura Peters And Ed Sperling - 23 Jan, 2025 - Comments: 0

Semiconductor Engineering sat down with Dan Brewer and Srikanth Kommu, co-CEOs at Brewer Science, to talk about current and future changes in materials used in semiconductor manufacturing and adjacent markets. What follows are excerpts of that conversation. SE: What was behind the decision to have co-CEOs instead of just one? Brewer: We see a lot of value to having multiple perspectives b... » read more

Improving GaN Device Architectures
By Katherine Derbyshire - 23 Jan, 2025 - Comments: 0

As the universe of applications for power devices grows, designers are finding that no single semiconductor can cover the full range of voltage and current requirements. Instead, combination circuits use different materials for different parts of the overall operating range. GaN is especially well-established in low-power applications like chargers for personal electronics, while silicon and... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Baby Steps Toward 3D DRAM
By Bryon Moyer - 17 Dec, 2024 - Comments: 0

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Challenges In Powering Electrification With GaN And SiC
By Katherine Derbyshire - 17 Dec, 2024 - Comments: 0

The wish list of device properties that designers of power management systems would like to have is lengthy, but no single material is yet sufficient for the full range of power control applications. For control transistors to handle power surges, breakdown voltages should be at least triple the expected operating voltage — 1.2 kilovolts or more for many electric vehicle applications, and ... » read more

NAND Flash Targets 1,000 Layers
By Bryon Moyer - 04 Dec, 2024 - Comments: 0

The chip industry is pushing to quadruple the stack height of 3D NAND flash from 200 layers to 800 layers or more over the next few years, using the additional capacity will help to feed the unending need for more memory of all types. Those additional layers will add new reliability issues a number of incremental reliability challenges, but the NAND flash industry has been steadily increasin... » read more

HBM Options Increase As AI Demand Soars
By Laura Peters - 21 Nov, 2024 - Comments: 0

High-bandwidth memory (HBM) sales are spiking as the amount of data that needs to be processed quickly by state-of-the-art AI accelerators, graphic processing units, and high-performance computing applications continues to explode. HBM inventories are sold out, driven by massive efforts and investments in developing and improving large language models such as ChatGPT. HBM is the memory of ch... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging
By Gregory Haley - 21 Nov, 2024 - Comments: 1

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

New Tradeoffs In Leading-Edge Chip Design
By Katherine Derbyshire - 21 Nov, 2024 - Comments: 0

Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available? Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet eve... » read more

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