category: Uncategorized

category: IoT, Security & Automotive

28nm Super Low Power CMOS
By Various Writers - 29 May, 2012 - Comments: 0

28nm Super Low Power (28nm-SLP) is the low-power CMOS offering delivered on bulk silicon substrate for mobile consumer and digital consumer applications. GlobalFoundries' 28nm-SLP process technology is designed for the next generation of smart mobile devices, enabling designs with faster GHz processing speeds, higher circuit density, lower standby power and longer battery life. The 28nm process... » read more

Issues In IP
By Ed Sperling - 07 Mar, 2012 - Comments: 0

Low-Power Engineering talks about challenges in IP with Neil Hand of Cadence, Navraj Nandra of Synopsys and Simon Butler of Methodics. [youtube vid=QQiYp2bN4qE] » read more

Something Old, Something Borrowed
By Ed Sperling - 11 Nov, 2011 - Comments: 0

The basic rule of SoC design is that it needs to be created relatively quickly, work as planned, and that it can be manufactured at a reasonable cost and with good yield ramp. That eliminates revolutionary changes on the technology side, limits the number of new materials, and relegates the most dramatic shifts to the business. That’s why most of the most far-reaching technology research i... » read more

3D’s Disruptive And Less-Disruptive Sides
By Ed Sperling - 26 Aug, 2011 - Comments: 0

The momentum behind vertical stacking of die, either in 2.5D or 3D configurations, is growing. So is the argument about just how big a change this will actually represent. To a large extent, it all depends on where you’re sitting. Xilinx CTO Ivo Bolsens calls 3D stacking a disruptive technology. From an FPGA standpoint, which potentially could be used as a programmable addition to any SoC,... » read more

Plenty Wise, Less Foolish
By Ed Sperling - 25 Aug, 2011 - Comments: 0

Selling more tools to fewer large customers has always seemed like a tough proposition for the tools industry. Remarkably, it seems to be getting easier. In fact, the more chipmakers push into advanced geometries, the more engineering managers are speaking up at industry conferences about a direct correlation between the number of tools they buy and the amount of time and money they save. Th... » read more

Manufacturing Closure with Calibre InRoute and Olympus-SoC
By Various Writers - 10 Feb, 2011 - Comments: 0

Achieving manufacturing signoff is getting more difficult at each node due to significant manufacturing limitations and variability. This paper from Mentor Graphics describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to d... » read more

Experts At The Table: Nice To Have Vs. Need To Have
By Ed Sperling - 10 Jun, 2010 - Comments: 0

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation. LPE... » read more

New Math: 1+1=1?
By Ed Sperling - 07 May, 2010 - Comments: 0

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

Experts At The Table: Verification Nightmares
By Ed Sperling - 23 Apr, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: Where does power fit in? N... » read more

New Forces For Consolidation
By Ed Sperling - 05 Mar, 2010 - Comments: 0

For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single... » read more

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