Closing The Performance Gap Between DRAM And AI Processors


As the workhorse of semiconductor memory, DRAM holds a unique place in the industry thanks to its large storage capacity and ability to feed data and program code to the host processor quickly. Lately, this unsung hero of the circuit board has been taking a backseat to its logic counterparts, as a wave of high-performance FPGAs, CPUs, GPUs, TPUs and custom accelerator ASICs emerges to meet t... » read more

eFPGA Architectural Improvements That Lower Test Cost And Increase Quality


More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA. As a result, we have gained extensive experience and knowledge in almost 10 years of doing eFPGA especially in production test for cost reduction and reliability improvement. eFPGA DFT and MBIST for high q... » read more

Causes Of Memory Unsafety


Memory unsafety is a characteristic of many of today’s systems. The root cause of buffer bounds vulnerabilities such as buffer overflows and over-reads is unsafe programming. Major software vendors consistently report memory unsafety problems. For example, the Chromium open-source browser project has stated that 69% of CVEs (Common Vulnerabilities and Exposures) reported relate to memory... » read more

Wireless Technology Insights: Navigating The Evolution From 5G To 6G


As 5G evolution advances, developments like the open radio access network (O-RAN) ecosystem, non-terrestrial network (NTN) infrastructure, and 5G reduced capability (RedCap) devices continue to gain momentum. Though 5G implementation is still underway, the wireless communication industry is already preparing for next-generation 6G wireless technology. With so much development happeni... » read more

AI Testing AI: The Future Of 6G Test


The impending arrival of 6G technology promises to revolutionize the way we connect and communicate. With expected data rates of up to 100 times faster than 5G, 6G is poised to enable unprecedented applications, from augmented reality (AR) and virtual reality (VR) to real-time remote surgery and autonomous vehicles with ubiquitous connectivity. A significant facet of 6G's potential lies in the ... » read more

Protecting Highly Confidential Data In IoT Devices


How should we approach the protection of highly confidential security parameters and personal data? It's just like our daily routines: when we leave home, we lock the door and take care not to lose the key. Similarly, in the realm of cybersecurity, safeguarding cryptographic keys is paramount. No matter how robust your data protection system is, it's rendered ineffective if keys or passwords... » read more

Texas: Cybersecurity Workforce Resilience And eCTF Success


Workforce resilience, the ability to adapt and recover from challenges, is a MITRE Engenuity priority. To ensure a resilient cybersecurity workforce that can defend organizations and the entire nation, we know that future professionals need to be interested in the field. As such, each year we proudly present Embedded Capture the Flag (eCTF), a two-phase competition for students to both test an... » read more

The Challenge And Value Proposition of eFPGA Emulation


More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are already working in silicon. Big customers like Renesas are planning high volumes and families of chips using eFPGA. eFPGA is being used in process nodes from 180nm to 5nm, with 3nm and 18A in evaluation. Especially for the high-volume customers working in advanced finFET nodes, the strong need is for first ... » read more

Formal Verification Best Practices: Investigating A Deadlock


To ensure a design is deadlock free with formal verification, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the current state and the number of cycles we must wait, in the future the design must respond. This translates very nicely using a type of SystemVerilog Assertion called “liveness propertie... » read more

Unlocking Efficiency: The Power Of IP Blocks In Silicon Chip Design


The fastest, most efficient and cost-effective way to design silicon is by leveraging intellectual property (IP) blocks. This methodology reduces risk, allows a design team to focus on its own differentiation, and allows scalability. Re-using existing IP offers even more value for design teams. But not every company has embraced the approach. Here’s why you should consider it. To optimize ... » read more

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