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Observation Post


By Pranav Ashar After attending the 2013 Design and Verification Conference (DVCon) in San Jose, Calif., I have compiled notes as both an observer and a panel participant. Here are my observations: Wally Rhines, CEO of Mentor Graphics, gave the keynote presentation: Accelerating EDA Innovation Through SoC Design Methodology Convergence. Logically and effectively he made the case that SoC in... » read more

Is This The Era Of Automatic Formal Checks For Verification?


I was thinking about the above question and recalled something IBM would repeat annually back in the late 1980s about its OS/2 replacement for MS-DOS. “This is the year of OS/2!” they would shout. But the marketplace wasn’t listening. As one buddy of mine liked to say, it was only half of an operating system (O.S./2). In the last nine months, my company, Real Intent, along with our com... » read more

Experts Panel And Tutorial At DVCon


Besides our usual exhibit at the Design and Verification Conference in Santa Clara at the end of next month, Real Intent has organized a panel and a half-day tutorial that highlights some of the changes happening in our industry—and which may have been overlooked. The panel addresses the interesting topic “Where Does Design End and Verification Begin?” The abstract states that design a... » read more

Clocks And Bugs


In late September, I blogged about the results of the 2012 DAC survey on CDC bugs, X propagation, and timing constraints by Real Intent. Now for those of you who don't remember what CDC means, it is an acronym for clock domain crossing. In modern SoCs, the number of different clock domains can easily exceed 100, due to the integration of different blocks and IP, each with their own clock. Not ... » read more

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