category: Videos

category: IoT, Security & Automotive

Zero Trust Security In Chip Manufacturing
By Ed Sperling - 08 Feb, 2023 - Comments: 0

More equipment vendors and more IP are making the data in a fab much more valuable than in the past, and a potential target for hackers. What’s needed is a different approach to architecting and deploying services and equipment, so breaches can be stopped before they affect other equipment and data, and a better way of sharing data. Brian Buras, production analytics solution architect at Adva... » read more

Efficient Trace In RISC-V
By Ed Sperling - 19 Dec, 2022 - Comments: 0

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what's needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are tak... » read more

Silent Data Corruption
By Ed Sperling - 12 Dec, 2022 - Comments: 0

Defects can creep into chip manufacturing from anywhere, but the problem is getting worse at advanced nodes and in advanced packages where reduced pin access can make testing much more difficult. Ira Leventhal, vice president of U.S. Applied Research and Technology at Advantest America, talks about what’s causing these so-called silent data errors, how to find them, and why it now requires ma... » read more

Automated Optical Inspection
By Ed Sperling - 07 Nov, 2022 - Comments: 0

Building good automated models for inspection require more data to be collected, both good and bad. Vijay Thangamariappan, R&D engineer at Advantest, explains how to develop models for automating optical inspection, using a multi-thousand pin socket as an example for how machine learning has helped reduce the return rate due to defects from 2% down to zero. He also explains how to achieve t... » read more

Deep Learning In Industrial Inspection
By Ed Sperling - 24 May, 2022 - Comments: 0

Deep learning is at the upper end of AI complexity, sifting through more data to achieve more accurate results. Charlie Zhu, vice president of R&D at CyberOptics, talks about how DL can be utilized with inspection to identify defects in chips that are not discernible by traditional computer vision algorithms, classifying multiple objects simultaneously from multiple angles and taking into accou... » read more

Total Critical Area For Optimizing Test Patterns
By Ed Sperling - 19 Oct, 2021 - Comments: 0

Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in th... » read more

Growing Challenges With Wafer Bump Inspection
By Ed Sperling - 11 Oct, 2021 - Comments: 1

As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

Optimizing AI Systems
By Ed Sperling - 29 Sep, 2021 - Comments: 0

Inserting AI and machine learning into chips adds a whole new dimension of complexity, and creates a variety of potential problems, including deadlocks, loss of performance, and difficulty in achieving closure on many fronts. Gajinder Panesar, fellow at Siemens EDA, talks with Semiconductor Engineering about what’s changed and how to optimize these new devices and systems by monitoring them f... » read more

Design For Test Data
By Ed Sperling - 14 Jul, 2021 - Comments: 0

As design pushes deeper into data-driven architectures, so does test. Geir Eide, director for product management of DFT and Tessent Silicon Lifecycle Solutions at Siemens Digital Industries Software, talks with Semiconductor Engineering about a subtle but significant shift for designing testability into chips so that test data can be used at multiple stages during a device’s lifetime. » read more

Monitoring Performance From Inside A Chip
By Ed Sperling - 01 Jun, 2021 - Comments: 0

Deep data, which is generated inside the chip rather than externally, is becoming more critical at each new process node and in advanced packages. Uzi Baruch, chief strategy officer at proteanTecs, talks with Semiconductor Engineering about using that data to identify potential problems before they result in failures in the field, and why it's essential to monitor these devices throughout their... » read more

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