Using data to target areas on a chip where defects are most likely to occur.
Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in these designs, and how to optimize test patterns to be able to quickly target those areas with tests.
Less precision equals lower power, but standards are required to make this work.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
Ensuring that your product contains the best RISC-V processor core is not an easy decision, and current tools are not up to the task.
Wafer manufacturing and GPUs draw investment; 106 companies raise $2.8B.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
How prepared the EDA community is to address upcoming challenges isn’t clear.
Advanced etch holds key to nanosheet FETs; evolutionary path for future nodes.
Details on more than $500B in new investments by nearly 50 companies; what’s behind the expansion frenzy, why now, and challenges ahead.
From specific design team skills, to organizational and economic impacts, the move to bespoke silicon is shaking things up.
Less precision equals lower power, but standards are required to make this work.
New memory approaches and challenges in scaling CMOS point to radical changes — and potentially huge improvements — in semiconductor designs.
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
Leave a Reply