Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes.
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Drew Wingard peels back the covers on dark silicon, the next big thing in semiconductors and what's needed to get there in a candid discussion with System-Level Design.
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Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening.
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Bernard Murphy talks with System-Level Design about what's changing in the semiconductor design area, how 3D stacking will affect design and what's needed in EDA tools.
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eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.
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Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.
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System-Level Design talks with Mentor Graphics, Cadence, and an Accellera member about what's changing in verification--and where the missing pieces are.
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System-Level Design digs into the future of the design automation tools industry and the Design Automation Conference with Cadence's Neil Hand, Atrenta's Mike Gianfagna and Springsoft's Johnson Teng.
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System-Level Design talks with Bob Bluth of the Naval Postgraduate School about UAV design and debug challenges--and what's inside of these devices. (The blue and green cellophane tape seal some of the access points prior to delivery--and the directions).
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Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm.
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Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.
Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.
The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?
eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.
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