category: Videos

category: IoT, Security & Automotive

Improving Edge Inferencing
By Ed Sperling - 02 May, 2019 - Comments: 0

Cheng Wang, senior vice president of engineering at Flex Logix, talks with Semiconductor Engineering about how to improve the efficiency and speed of edge inferencing chips, what causes bottlenecks, and why AI chips are different from other types of semiconductors. » read more

Complexity’s Impact On Security
By Ed Sperling - 01 May, 2019 - Comments: 0

Ben Levine, senior director of product management for Rambus’ Security Division, explains why security now depends on the growing number of components and the impact of interactions between those components. This is particularly problematic with AI chips, both on the training and inferencing side, where security problems on the training side can alter models for AI inferencing. » read more

Verification At 7/5nm
By Ed Sperling - 25 Apr, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

Safety-Critical Coverage
By Ed Sperling - 24 Apr, 2019 - Comments: 0

Dave Landoll, solutions architect at OneSpin Solutions, discusses verification in safety-critical designs, why it’s more of a challenge in automotive than in avionics, and why verification of these systems includes what the system should not be doing as well as what it should be doing. https://youtu.be/Ze3WwEARfx0 » read more

Multi-Physics At 5/3nm
By Ed Sperling - 11 Apr, 2019 - Comments: 0

Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

GDDR6 – HBM2 Tradeoffs
By Ed Sperling - 10 Apr, 2019 - Comments: 0

Steven Woo, Rambus fellow and distinguished inventor, talks about why designers choose one memory type over another. Applications for each were clearly delineated in the past, but the lines are starting to blur. Nevertheless, tradeoffs remain around complexity, cost, performance, and power efficiency.   Related Video Latency Under Load: HBM2 vs. GDDR6 Why data traffic and bandw... » read more

Safety Critical Design In Automotive
By Ed Sperling - 03 Apr, 2019 - Comments: 0

Shiv Chonnad, hardware engineer at Synopsys, examines how to design chips for safety-critical applications such as automotive and ensure they work as planned and in accordance with ISO 26262 and the various ASIL levels. This includes how to find faults at both a chip and a system level. https://youtu.be/3dL4ZuSe5Ls » read more

Billion-Gate Design Connectivity
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Debug Changes At Advanced Nodes
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a commensurate amount of software complexity. The key is how to maintain or reduce time to market, and that requires a different way of approaching the problem. » read more

2.5D, 3D Power Integrity
By Ed Sperling - 14 Mar, 2019 - Comments: 0

Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

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