Tech Talk: Getting To The Next Node


IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

ESL Challenges


System-Level Design talks about the challenges of ESL with Cadence's Ran Avinun, Synopsys' Johannes Stahl, Mentor Graphics' Thomas Bollaert and Forte Design Systems' Brett Cline.   [youtube vid=HftMM71Epqo] » read more

Roundtable: Battery Life Vs. Delay


Low-Power High-Performance Engineering talks about the challenges of dealing with latency in semiconductor design with Andrew Caples of Mentor Graphics, Chris Rowen of Tensilica, Drew Wingard of Sonics and Larry Hudepohl of MIPS Technologies. [youtube vid=Q_opQ3W9esA] » read more

Increasing Levels Of Risk


Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

Tech Talk: LP Design And Verification


Cadence's Qi Wang talks with Low-Power/High-Performance Engineering about power formats and what else can be done to save power in SoCs. [youtube vid=afJ6VQ0AYgg] » read more

The Growing Verification Challenge


System-Level Design talks with Charles Janac of Arteris, Frank Schirrmeister of Cadence, Venkat Iyer of Uniquify and Adnan Hamid of Breker Verification Systems about the growing difficulty of verifying complex SoCs and what lies ahead. [youtube vid=zUB4_t9teE8] » read more

The Return Of RC Delay


Semiconductor Manufacturing & Design talks with Mehul Naik of Applied Materials about why RC delay has become a hot topic again, and what will be necessary to solve it. [youtube vid=aQjqcpZWi0A] » read more

Roundtable: Lower-Power Chips


Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

Tech Talk: Faster But Less Accurate


Semiconductor Engineering talks with professor Jan Rabaey of the University of California at Berkeley about new design approaches that could significantly boost performance and simplify design and verification—for some applications. [youtube vid=hAk1xA56h_A] » read more

Changes Ahead


Semiconductor Manufacturing & Design talks with GlobalFoundries EVP Mike Noonen about future challenges in IC manufacturing, the future of stacked die and ecosystem challenges ahead. [youtube vid=Wdp9JYvBeSk] » read more

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