The Challenge Of Packaging

Most semiconductor designers would like to forget about the package. It’s not possible anymore.

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Semiconductor packaging isn’t a sexy subject, and it’s one that’s been largely overlooked by the design community. Until now, that is.

I recently spoke with Brad Griffin at Cadence, who stressed that managing the power through packages even on a single die is still one of the most challenging things engineers must navigate.

“As people integrate more technology into a single chip or even a stacked die without 3D IC, how to manage that still seems to be the leading problem that our customers are dealing with. And they’re trying to do it on as few layers as possible and on the cheapest materials possible, using the cheapest attach method possible,” he said.

He thought that when PCI Express first hit the market at 2.5GBps it wouldn’t be possible to use a wire bond package, and was surprised when it happened. “Now they are at 5 and 10 GB, and they are still trying to do it with a wire bond. It amazes me that we keep on falling back and finding ways. It’s either through tolerance inside the chip, because you can capture the data with signals that aren’t as clean, or they are more tolerant in stability in power fluctuations. We just keep finding ways to manage that.”

The challenges remain the same, namely how to make sure to get enough power to the device so that it can do what it needs to do. Things just keep getting smaller, Griffin said. “If you look at the layers on these packages, its not like it’s a solid power plane. It’s like Swiss cheese. How do you return the current back through that Swiss cheese mess when you are trying to drive a DDR4 signal running at 4GBps? And that’s 64 bits.”

“With speeds getting faster, all the little things that we’ve been able to not worry about, we have to start worrying about. And we’re not being blessed with the fact that now we’ll have to move to this new material or now we’ll finally accept that this package has to get more expensive add more layers to it. No one is ever comfortable with that,” he observed.

Continuing to reduce the cost of the packaging while meeting these high-speed design constraints seems to be the most challenging thing that we have from a power perspective and a signal integrity perspective.

 

~Ann Steffora Mutschler