Chip Failure? Don’t Worry About It!

The surprising number of design insights you can get from staring at a cat.

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By Ron Craig
Here in the United States it’s tax time again. Along with every other loyal taxpayer, I’ve been working on identifying every conceivable deduction I can think of to minimize my overall tax burden. I’m not an expert on tax law, but as far as I can tell I still can’t take advantage of the non-tax deductible dependents we like to call ‘the cats.’

Our own demanding house guests survive on roughly 20 hours sleep per day, and spend the rest of their time either engaged in random acts of madness or consuming food that appears to cost more per ounce than my car. That being said, I do have to hand it to them. They are the masters of stress-avoidance. Granted, they haven’t exactly amassed any possessions during their short lives, and they’ve hardly ventured more than 10 yards from the front door, but as I hack my way through my ‘to do’ list I can’t help feeling that it wouldn’t be so bad to swap roles with them for a day.

 

Fig. 1: Cat

Fig. 1: Cat

I attended an interesting panel session at DesignCon recently that touched on how project teams tend to take the opposite approach to ‘the cats,’ amplifying rather than avoiding stress. A myriad of issues can delay tapeout, and the panel discussed the measures they have taken (or would like to take) to avoid these issues. What it often came down to in the end was that there are always better ways of doing things, but barriers to better methodologies persist. Design teams continue to struggle with inconsistent use of design tools across their organizations, for example, which make handoffs and co-operation more difficult. It’s hard to focus on these methodology issues when faced with the relentless search for ‘best in class’ tools, however. For their part, EDA vendors often make the problem worse due to their inconsistent and incomplete adoption of standards—often seeking to exploit a standard as a competitive advantage rather than a means of growing the overall pie.

One of the more compelling questions asked by the panel moderator (Ed Sperling of System-Level Design) was if it was possible to further shrink project schedules. One panelist noted how his most recent project was three months ‘from concept to tapeout,’ which is an incredibly short time. He further pointed out that such an aggressive schedule could only be achieved through extensive IP re-use. And it’s not just the IP itself. What about the ancillary data such as timing constraints, verification environments, etc.? Timing constraints were acknowledged to be a particular burden, especially because bad ones cannot only slow tapeout but hide issues until they pop up in the field. There are a lot of issues to balance, but at least one company is proving it can be done.

The good news is that these issues (to quote a former government figure) are ‘known unknowns’ rather than ‘unknown unknowns’ and a variety of creative solutions are regularly being put in place across the industry to mitigate them. Chip failures may be something that we continue to worry about, but at least we’re becoming better at stress-avoidance.

–-Ron Craig is senior marketing manager at Atrenta.


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