Constraints typically don’t undergo the same level of verification before being used even though they’re error prone and nearly impossible to manage.
A design goes through several transformations in a typical register transfer level (RTL) to layout flow, and a variety of verification techniques are employed (simulation, equivalence checking, etc.) to ensure that its intent has not changed. It’s normal for timing constraints to be created and refined in parallel with the RTL and netlist throughout the design cycle, but these constraints typically don’t undergo the same level of verification (or indeed any verification) before being used. The creation and refinement of constraints is largely a manual, error- prone and time-consuming process, and managing thousands of lines of timing constraints throughout the flow is nearly impossible. Subsequently, constraint problems pose a serious risk to the success of the implementation process. Poor constraints impact overall chip quality and delay timing closure. In the worst case, incorrect constraints can result in a silicon failure and re-spin. There is a critical need for an EDA solution to ensure timing constraints are valid throughout the design flow.
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