Constraints typically don’t undergo the same level of verification before being used even though they’re error prone and nearly impossible to manage.
A design goes through several transformations in a typical register transfer level (RTL) to layout flow, and a variety of verification techniques are employed (simulation, equivalence checking, etc.) to ensure that its intent has not changed. It’s normal for timing constraints to be created and refined in parallel with the RTL and netlist throughout the design cycle, but these constraints typically don’t undergo the same level of verification (or indeed any verification) before being used. The creation and refinement of constraints is largely a manual, error- prone and time-consuming process, and managing thousands of lines of timing constraints throughout the flow is nearly impossible. Subsequently, constraint problems pose a serious risk to the success of the implementation process. Poor constraints impact overall chip quality and delay timing closure. In the worst case, incorrect constraints can result in a silicon failure and re-spin. There is a critical need for an EDA solution to ensure timing constraints are valid throughout the design flow.
To download this white paper, click here.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
Applied Materials’ VP looks at what’s next for semiconductor manufacturing and the impact of variation, new materials and different architectures.
Researchers digging into ways around the von Neumann bottleneck.
iPhone X elevates niche optical technology to hot growth market. Now the question is what else it is good for?
Optimizing complex chips requires decisions about overall system architecture, and memory is a key variable.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.
Stacking die is garnering more attention, but design flows aren’t fully ready to support it.
What hoops will designers have to jump through to avoid concurrency bugs?
Maximum flexibility is no longer the reliable path to product success. While flexibility must be there for a purpose, it also can be a liability.
Why managing power is becoming more difficult, more critical, and much more expensive.
This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.
Accuracy is a relative term that complicates design and verification. Machine learning makes the industry face some of those realities head on.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply