How to avoid costly re-spins due to CDC-related bugs.
Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains. Clock domain crossing (CDC) signals, those which traverse these domains, are often subject to metastability effects that can cause functional errors. Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify correct data transfer across clock domains. As a result, many CDC-related bugs go undetected until the post-silicon verification stage, necessitating costly re-spins. The Cadence JasperGold Clock Domain Crossing App provides a complete solution that automatically infers CDC intent from the design and comprehensively analyzes structural, functional, and reconvergence issues. The JasperGold CDC App also provides an integrated debug environment with advanced debugging options.
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