Co-Modeling Takes Emulation To The Next Level: System-Of-Systems

Understanding co-modeling technology, its impact on verification and validation, and what are the best tradeoffs.


As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended.

Today’s most advanced emulators enable SoS verification with the help of an advanced capability called co-modeling. As the predominant emulation use model evolves from in-circuit emulation (ICE) to virtual emulation, co-modeling technology is necessary for performing HW/SW co-verification and debug while maintaining the required high emulation performance.

Any new applications running in emulation must be competitive with ICE throughputs (roughly 1,000 times faster than software simulation environments) to succeed. To do so, they must ride on a state-of-the-art co-modeling methodology; thus achieving fast wall clock speed, high throughput, versatility, and advanced modeling support.

Thus demand for co-model channel versatility and performance increases as new virtual applications and test platforms emerge for new emulation targets. For today’s emulators to be viable, they must have wide solutions support, fast throughput, and advanced co-modeling capabilities to meet new and emerging application demands for complex SoS designs.

Understanding co-modeling technology, its impact on verification and validation, and how best to make trade-offs should be a critical aim for anyone selecting and deploying emulation co-modeling resources. Let’s explore how emulation co-modeling is architected to meet the needs of advanced verification and validation, improving time to market across a wide range of vertical solutions; including networking, storage, multimedia, mobile, automotive, wireless, and cellular.

Co-model architecture
Co-modeling is an untimed, transaction-level interface to the emulator expressed as function calls per the Accellera Standard Co-Emulation Modeling Interface (SCE-MI). Co-modeling supports design dynamic configuration, streaming waveforms and simulation data, and conveying the IO data from virtual devices and transactors to and from the design during emulation. Co-modeling also improves a wide range of significant test capabilities in the areas of functionality, performance, debug, power analysis, design for test (DFT), coverage, software co-verification, and interoperability of systems, which in turn improve time to market.

Co-model channels are very high-speed, low latency, high bandwidth channels, equivalent to PCIe. Co-model channels follow the same producer-consumer models employed by any IO subsystem in a computer architecture. However, there is one major difference. Unlike most IO designs, co-model channels should not be highly tuned at the expense of all other traffic types. For example, a streaming interface and a message-based interface have very different requirements when it comes to throughput and latency tradeoffs, and they can work against each other depending on the protocol. Therefore, an architecture that is flexible and tunable to each particular vertical solution must be deployed in order to meet the wide and demanding plethora of IO requirements posed by current and future applications.

Developing a superfast co-model channel would be a waste if either the emulation OS or HW platform components become overwhelmed. Naturally, a balanced system is always desired. Conversely, as data plane traffic increases, channel performance can become the bottleneck for the HW platform performance. Consequently, there are several aspects to consider when designing co-model channels; such as producer and consumer rates, channel throughput, and the network of compute elements, or mesh. The wires or virtual wires that interconnect the mesh can be referred to as a network. In fact, a co-model channel can be viewed as a network of any type.

Figure 1. Emulation Co-model Dimensioning

Additionally, when channels saturate, to relieve the saturation the emulator must be able to scale in terms of emulation HW, SW/OS, and co-model channel elements as the DUT scales. The alternative is to stop the emulation clock to let these elements “catch up,” which then negatively affects wall clock throughput for the jobs that are attempting to complete on the emulator. Well thought out architectures scale to the workloads imposed upon them. Let us consider each of these factors when considering co-model architectures that can deliver optimal performance and scalability.

Advanced applications and performance tuning
Co-model channels get used for much more than just stimulus, as shown in Figure 2. They can be used for debug by employing a number of mechanisms where co-model data streaming to an unlimited depth for signal access is possible, and they can be used for advanced methodologies like power and DFT. For example, metadata can be exchanged between the emulator and the software for application layer interlock, or data can be extracted from the design that can be used in a verification methodology like UVM monitors and functional coverage. Coverage data (dynamic coverage closure) can also be extracted for other kinds of analysis, like system-level performance, fault injection, and cryptographic hardness.

Figure 2. Typical Solution Block Level Diagram

It is noteworthy that in analysis or optimization modes, specific and custom data exchanges through software can be easily deployed by users. These include data streaming, $display, and different kinds of I/O operations that are hardware description language (HDL) specific. These are typical use models for the link between any Veloce emulator and a co-model host machine today. Co-model channels are far more than just the optical links they ride on. They have a lot of SW stack and OS level compartmentalization for using data in creative and advantageous ways. For example, highly efficient methods are used between caller/callee and between transactions to maximize data movement and minimize wall clock time per interaction.

These channels can also be heavily involved in a creative SW debug methodology. Offline debug of processors, hybrid systems and communication links between software and the DUT allow for advanced debug and waveform streaming iterations. Co-models can be used in conjunction with virtual or HW based JTAG probe methodologies. They also provide specific SW protocol analyzers for any number of protocols in a variety of applications, including storage, networking, Wi-Fi, cellular, automotive, multimedia, and mobile.

All application software capabilities are built on top of the co-modeling software. Take the case of networking where virtual Ethernet solutions are assembled using the co-model channel SW API. This requires distributed communications, high-throughput streaming, and large numbers of input/output ports to accommodate tens of Terra Bytes of networking stimulus and traffic analysis per SoC. Clearly, in this case channel throughput ought to be tuned for maximum streaming throughput, whereas prioritizing on latency would be more pertinent for PCIe throughput of posted transactions. Even better, one co-model channel can be optimized for a specific traffic type (like streaming) while another channel can be tuned for another profile (like transactional). This offers a highly flexible and optimized platform that achieves maximum verification throughput per application to accelerate verification closure.

Co-model deployment: Strategy and semantics
The Veloce Strato co-model SW infrastructure built around Mentor’s optical channel hardware is the main element used to address a wide variety of solutions that solve many different problems. Veloce’s co-model SW was designed using the Accellera SCEMI-2.4 standard and the SystemVerilog Direct Programming Interface (DPI), shown in Figure 3. The Veloce Strato co-model SW was written to be application agnostic through an extensive API with performance in mind.

The transactors built on top of these channels are then used to build higher-level standalone applications, virtual machines, and infrastructures using QEMU and Vbox. The success of building virtual applications ultimately rests on the strength of the co-modeling technology.

Having consistent technology and performance curves over port counts and channels permits all Veloce applications to be constructed in the same way, freeing emulation design teams from “one off” developments. Unlike other platforms, Veloce Strato enjoys seamless portability between simulation and emulation because of its strict SW/OS adherence to open Accellera SCEMI standards and Language Reference Manual (LRM) definitions across all co-model applications developed and deployed on Veloce emulators.

Figure 3. SCEMI Transaction Transport Use Models

However, there is more to this than data plane scaling in HW. SW can soon become the bottleneck as well. The control plane is no less important when dealing with streaming and non-streaming data flows. Mentor has created very smart SW constructs and other innovative semantics that allow host applications and emulation to run in parallel. In this way, SW overheads can be pipelined with emulation HW execution. Organizationally, co-modeling has been designed from the ground up to fit well into both the Veloce Strato HW system and its OS in order to achieve this high degree of execution parallelism. The co-modeling software and OS are indeed tightly interdependent to achieve working set pipelining between SW applications and emulation HW.

Anyone who has designed IO subsystems understands the pitfalls of generalizing an IO architecture. Following this progression, what is true of co-modeling for solutions is also true for state-of-the-art visibility features that are designed to use co-model channels. Visibility has its own peculiarities and specific performance objectives as a traffic profile. A balanced processing mesh, memory, storage, and co-model channel utilization are critical elements for a fast time-to-visibility emulation experience.

As a necessary part of emulation technology, co-modeling services advanced virtual applications in networking, storage, automotive, Wi-Fi, cellular, multimedia, mobile, CPU, Hybrid Systems, and many other applications. It also remains the standard methodology for advanced testbench-driven verification and debug, UVM, power analysis, DFT, design check pointing, and security.

The co-model technology is central to Veloce Strato’s core design to the extent that the Veloce Strato platform has been architected to achieve the highest verification throughput per solution. Veloce Strato’s versatile and high-performance co-modeling channels are essential for meeting or improving time to market goals, especially for complex SoS designs.

To learn more about how co-modeling can take your design and verification to the next level, read the whitepaper Co-modeling: A Powerful Capability for Hardware Emulation.

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