Cognichip: Using AI To Speed Complex Chip Design

AI software innovation is accelerating, while the chip design process is struggling to keep pace due to rising complexity and physical constraints. The big challenge now is how to close that gap.

The solution is at least as complex as the hardware design. It requires much greater reuse of IP, along with portions of existing designs, so that not everything needs to be created from scratch. AI needs to be trained to tackle both mundane and complex tasks. And all of this needs to happen quickly and cheaply enough to develop customized solutions that are not overly pessimistic and redundant.

Enter Cognichip, a startup that emerged from stealth mode in May 2025. “We’re building Artificial Chip Intelligence (ACI) that essentially can understand, learn, and solve chip design problems,” said Stelios Diamantidis, the company’s chief product officer. “We train it with RTL, we train it with post-synthesis, netlist results. We train it with circuits. We even train it, of course, with aspects of specification and validation. But the idea is very simple. ACI understands and performs problem-solving tasks at a very high speed, and most importantly, at very high parallelism.”

One of the challenges in designing these complex chips is that they are highly customized and extremely expensive, sometimes costing more than $100 million per design.

“The first thing that needs to happen is to get the cost of design under control,” Diamantidis said. “We live in a world where a single individual, if not a small team of folks, can launch a new software product with super elaborate capabilities and very little effort in little time. Yet all this stuff runs on hardware that generally was designed at least three or four years ago, which is the time it takes to come up with an idea, design a new chip, and then get to volume production, let alone a system socket. That’s three years, a $100 million plus investment, and committing a team of experts for the period of time needed to get that chip out to market. And then, in addition to dealing with constraints for three or four years, when this chip hits the application, is it going to be the right chip, or will this application that gets written in weeks require something else? So that investment is basically suffering from a sub-optimal fit to market requirements.”

Cognichip’s approach is to develop a physics-informed foundation model that achieves more parallelism than is available in existing development flows so that some of the margin can be removed from designs. “We’re very happy using today’s abstractions, but we need to manipulate them at a much higher bandwidth,” Diamantidis said.

Diamantidis sees Cognichip serving the broader semiconductor market in three ways. “Established semiconductor leaders have a lot of expertise, they have a ton of resources, and also a lot of available prior designs and capability,” he said. “But for them, it’s an efficiency game. They’re looking to take their design teams to do the next derivative, or the next shrink of a design, to go after a very targeted market. Doing more with less is the name of the game when it comes to some of these leaders. Then, if I go one notch further, maybe we have mid-range companies — and those mid-range companies already have very capable teams and a lot of expertise — but maybe they’re looking to acquire incremental expertise to build something in an adjacent market, or to be able to achieve a device that maybe in the past has been beyond their ability or their budget. So it’s still doing more with less, but adding expertise, adding the dimension that’s missing from the team to be able to execute to the next level. And then finally, we have startups looking to stage up new teams and get to market proof very quickly. Speed and flexibility are key.”

Cognichip, based in Redwood City, California, launched with $33 million in seed funding from Lux Capital, Mayfield, FPV, and Candou Ventures.