Cognichip: Using AI To Speed Complex Chip Design


AI software innovation is accelerating, while the chip design process is struggling to keep pace due to rising complexity and physical constraints. The big challenge now is how to close that gap. The solution is at least as complex as the hardware design. It requires much greater reuse of IP, along with portions of existing designs, so that not everything needs to be created from scratch. AI... » read more

Startup Funding: Q2 2025


Investors were drawn to a wide range of innovative approaches in Q2 2025, backing startups developing superconducting logic, chips for an emerging number format, big data processors, and novel power semi architectures. At the same time, photonics continues to draw investment dollars due to its ability to move data faster and with less energy at both the chip-to-chip and data center levels. T... » read more

Formal Verification Of A Mixed Signal IP with Both Digital And Analog Blocks


A new technical paper titled "Analogous Alignments: Digital "Formally" meets Analog" was published by researchers at Infineon Technologies. Abstract: "The complexity of modern-day System-on-Chips (SoCs) is continually increasing, and it becomes increasingly challenging to deliver dependable and credible chips in a short time-to-market. Especially, in the case of test chips, where the aim is... » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)


A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more