Combining Power And Synthesis

By Ann Steffora Mutschler

Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow.

Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the process up a level of abstraction into high-level synthesis also has started gaining traction. What’s new is the inclusion of power management in both steps.

“Just like closing on timing or closing on area, closing on power is a responsibility of the synthesis tool including a high-level synthesis tool,” said Thomas Bollaert, product marketing manager for Catapult C at Mentor Graphics Corp. “Low power is becoming increasingly important on the designer’s radar screen and this is why they are asking more of the synthesis tool when it comes to low power.”

High-level synthesis can now be power-aware. While there are certain widely-adopted low-power techniques – such as clock gating, which is critical to understanding how much dynamic power can be saved – that designers typically use and implement when doing manual RTL coding, these can take a lot of time to do by hand and can be error-prone. High-level synthesis has the potential of making the analysis and the transformation automatically on behalf of the designer thereby generating much more power-efficient designs.

Gal Hasson, senior director of marketing for synthesis, power and test automation at Synopsys, said this is all about time to results. “If you start optimizing as soon as you start synthesis you end up with better results. For many years customers have been doing MCMM (multi-corner, multi-mode) in place-and-route only. When that is started in synthesis, better results are achieved. Power can no longer be an afterthought.”

Another key to making sure the best results are reached is a tight interaction between synthesis and place-and-route. “When you’re doing a lot of low-power design, you’re doing a lot of clock gating, or you’ve got physical considerations… If all you’re doing is thinking about low-power on the RTL side or the synthesis side and then you throw it over the wall to a totally different tool or totally different group, a lot of the optimizations that you planned in the RTL might not work out,” said Rob Knoth, senior product manager at Magma Design Automation.

While the majority of semiconductor designers are seriously looking at power, they are also trying to figure out what they can do to manage it in the context of their overall design goals, said Jack Erickson, a member of Cadence Design Systems’ Encounter Digital Implementation marketing group. There are plenty of techniques available today for minimizing power, but ultimately designers have goals in terms of meeting a performance spec, a die size and achieving time-to-market, so it comes down to how they manage all of these things and get their chips out the door, he said.

In response to this, in Cadence’s synthesis tool, as with most synthesis tools on the market today, power is not a separate tool or even a separate step within the tool. “When you look at power versus performance, they trade off versus each other orthogonally, and we don’t want our customers to try to have to manage that manually because they’ll never get their chip out the door in time,” said Erickson. “So we built power awareness in.” Cadence includes the notion of cost functions so that when logic is structured it is done so for performance and using cost functions such as area, leakage power and dynamic power. As a result, everything is considered simultaneously as the logic is being built.

To address leading-edge design concerns, Mentor’s Bollaert said customers are now asking for dynamic voltage frequency scaling. That allows a system to use a different voltage or clock frequency and slow down a design so it consumes less power. As power consumption is a function of frequency and a function of voltage squared, if the frequency is reduced, the voltage is lowered, and this can reduce power consumption.

“Doing this is simple when you look at the math, but doing this in hardware is actually very complicated because the proper intelligence is needed in the system to determine when to slow down the design, when to slow down the clock, and when to reduce the voltage. In order to make an intelligent decision, sufficient information about what each of the subsystems are doing and so forth is also needed. It truly requires designing up front for dynamic voltage and frequency scaling, and it also requires fine-tuning intelligence on when to drive the right frequency and voltage. This is truly an advanced low-power design technique. Few are doing it, some are exploring it, and many would like to be able to do it,” he said.

ST-Ericsson used Mentor’s previous-generation Catapult C low-power technology to reduce the area of IP by approximately 30%, according to ST-Ericsson. With new capabilities, Mentor claims a 70% reduction in power consumption for a different customer using Catapult’s clock gating capabilities.

Magma’s Knoth is hearing the same kinds of demands from customers. From the synthesis perspective, making this happen requires a much more robust and multi-mode, multi-corner infrastructure, which is something that more synthesis tools have started doing, he said.

Going from one voltage domain to another requires a lot of extra logic such as level shifters and isolation cells. Knoth said Magma’s synthesis tool is able to consider that extra logic ahead of time, which is significant because those things take up a lot of area, and are typically slow.

“Level shifters and buffers are very slow cells and when Magma’s tool reads in the UPF or CPF, as you are synthesizing those paths, it will allow you to understand the timing and power impacts of all that extra logic,” he explained. “What users are really looking for is higher-level optimization in the RTL for power as well as better verification, because as you’re doing all these complex clock gating or higher-level RTL optimizations you are changing the logic. If you can’t verify it easily, no one is going to tape it out.”