Complete Transistor Level Electrical Checks With Formal Analysis

Nothing is worse for a design team than a chip that fails to work in the bringup lab. Electrical problems are historically a major cause of such failures. Power leaks, power-ground DC paths, missing level shifters, and design flaws such as high fanout lead to unexpected power consumption, incorrect functionality, and even total meltdown. Designers learned years ago that pre-silicon electrical checks on the transistor level netlist can detect many types of problems so they can be fixed before tapeout. However, traditional checking techniques have their limitations, so formal based methods play a crucial role for today’s designs.

Circuit designers have historically used a combination of good design practices, static netlist checking scripts, and SPICE/FastSPICE simulations to check for electrical issues. Scripts are hard to maintain as designs evolve and offer limited netlist coverage. Simulations can measure current and power draws beyond design margins, but they rely on design knowledge to generate vectors to accurately target potential design hazards on internal nets. Simulation also provides limited coverage. Designers would ideally like to leverage some sort of formal analysis technique that is easy to use and can provide complete coverage of the netlist.

Formal tools and methods for transistor level netlists are few, but symbolic simulation can do the job. When applied properly, this technique can formally simulate netlists without abstraction. It has been widely applied in formal equivalence checking of custom design functional descriptions against their structural netlists. Symbolic simulation has also been used by designers to uncover electrical hazards in their designs without the need to craft vectors targeting those flaws. This approach has been deployed successfully to check many types of custom circuit designs such as SRAM, ROM, CAM, standard cell libraries, and I/O pad cell libraries.

Fig. 1: Stimulus for binary versus symbolic simulation. (Source: Synopsys)

In symbolic simulation, symbols (logical variables representing values 0,1,x,z) are applied to the primary ports of the design, as shown in figure 1. These symbols propagate through the design, forming Boolean equations on each internal net. These equations are propagated and aggregated through the design, culminating in Boolean expressions on the output pins. These equations can capture logic behavior, power behavior, or any other aspect modeled in the simulation. There are three major advantages of symbolic simulation over more traditional methods:

• Vector-less: since the input for the symbolic simulation is an array of symbols, symbolic stimulus is generated automatically and no user vectors are needed
• High coverage: symbolic stimulus represents all possible combinations of inputs as well as all possible state transitions, so 100% design coverage can be obtained
• Debug vector generation: the simulator can provide the generated stimulus vector, binary waveform, violating devices, and other debug aids to quickly root cause a violation

Symbolic simulation can perform electrical hazard checks on a single power domain or multiple power domains, as well as glitch and dual glitch signal power integrity checks. There are many specific checks within these categories, including those for the following design hazards:

• DC power-ground shorts
• DC sneak path through power supplies
• High fanout
• High Beta ratio
• Deep transistor stacks
• Missing isolation clamps
• Floating gate induced power-ground (PG) power draw
• Missing level shifter induced PG power draw

After an electrical check violation has been detected in the design, it must be diagnosed and fixed. A symbolic simulator can provide a root cause binary stimulus vector that the designer can use to run a full Fast SPICE or SPICE simulation. A digital waveform in FSDB format specific to each violation can help with debug and analysis. A report in comma separated value (CSV) format details the nets and devices involved in the violation, and a trace report has information on the PG stack of the root cause devices. The GUI should include a schematic viewer, as in figure 2, showing the design hierarchy, the violating device/nets, and the violation database.

Fig. 2: Schematic highlighting nets and devices causing hazard. (Source: Synopsys)

All these capabilities make it much easier for the designer to diagnose and fix each violation. The only available solution providing all these debug features, as well as all the checks and other capabilities described earlier, is Synopsys ESP. It offers custom design formal equivalence checking based on symbolic simulation to achieve the ease of use benefits and high netlist coverage possible only with formal methods. It also offers pre-simulation and post-simulation waiver mechanisms to narrow down the violations to those of interest.

For high design quality, it is crucial to uncover electrical hazards with complete design coverage and fix them in a timely manner. A single Synopsys ESP symbolic simulation can analyze every circuit net in a netlist design and detect design violations in a few hours. This solution is increasingly used in the custom design space, and designers aiming to create a high-quality custom design should make symbolic simulation a must-have component in their tool portfolio. More information is available here.