Adding custom instructions to a processor without error-prone manual editing.
Processor customization is one approach to optimizing a processor IP core to handle a certain workload. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core.
In the past some processor IP vendors, notably ARC and Tensilica, offered extensible cores which allowed a limited amount of customization. However, with Codasip Studio, the processor architecture and microarchitecture can be described with the CodAL language, offering far more degrees of freedom both in terms of ISA and microarchitecture.
This CodAL ability is particularly synergistic with the RISC-V ISA, but it can be applied to cores based on any other ISA too.
The RISC-V instruction set has three classes of instruction. There is a base instruction set for a given wordlength (32-, 64- or 128-bit), different groups of optional standard extensions, and non-standard custom extensions.
RISC-V Modular Instruction Set. Source: Codasip.
There is a large part of the opcode space which is available for custom extensions. A processor architect can use such extensions to deliver extra processing performance to address a given computational workload.
Codasip offers off-the-shelf RISC-V processor cores which are licensed in the usual way with RTL, a testbench, and SDK. These cores can also be licensed in the CodAL source code which was used to design the cores and to generate the SDK and HDK. The CodAL source can be edited to create custom extensions and to modify other architectural features.
Microsemi used this approach on an audio design where they were seeking to replace a proprietary embedded core with a RISC-V one.1 They started with the base 32-bit instruction set but found that the cycle count was far too high. Adding the multiplication instructions improved performance but did not achieve their requirements. Finally, they worked with Codasip to create custom DSP extensions that significantly improved the performance 56x, with processor core gatecount growing 2.4x. Not only did they achieve their performance goal, but their codesize reduced from 232 kB to 64 kB, reducing the required instruction memory area 3.6x.
The Microsemi case: Reducing cycle count with custom RISC-V extensions. Source: Codasip.
Codasip Studio provides two approaches to implementing the custom instructions in hardware:
The legacy approach to adding new instructions to a core is based on manual editing. Adding custom instructions must be reflected in the following areas:
Design Automation without Codasip Studio. Source: Codasip.
With the software toolchain, intrinsics can be created so that the new instructions are used by the compiler, but this also means that the application code needs updating. However, modifying the existing ISS and RTL are both potential sources of errors. Lastly, if the verification environment needs changing, this is a further area for problems. Verifying these manual changes is a big challenge and adds risk to the design project.
Some vendors offer partially automated solutions, but by not covering all aspects of processor customization they still leave room for error due to the manual changes.
Design Automation with Codasip Studio. Source: Codasip.
In contrast, with Codasip the changes are only made to the CodAL source code. The LLVM toolchain is automatically generated with support for the new instructions. Similarly, the ISS and RTL are generated to include the custom instructions and can be checked using the updated UVM environment. This approach not only saves time, but is a more robust customization process. You can learn more on the topic in this paper, or explore Codasip Studio in more detail.
[1] Source: Implementing RISC-V for IoT applications, Dan Ganousis & Vijay Subramaniam, DAC 2017.
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