Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer
DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards.
The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in DesignWare uMCTL and uMCTL2 DDR memory controller IP products. This white paper will explain the concept of the read reorder buffer and explain how a read reorder buffer can improve memory bandwidth. It then concludes with experimental results showing how DRAM controllers with different architectures can achieve vastly different DRAM bus utilizations of 10%, 66%, or 100% from the same input traffic stream, depending on whether the architecture has no RRB, an RRB with external scheduling, or an RRB with content-addressable memory (CAM)-based scheduling.
To download this white paper, click here.
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