Demystifying Mirror Types

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of mirroring which are used in different places. Often, I get questions about what, exactly, those differences are. And even more, why the styles are used for different objects in your layout.

Today, I hope to be able to clear up any confusion because if you’re working with complex stacked-die designs with discrete components, die stack layer types, embedded components, this is more important than ever before. You want to be sure that your 3D rendering is accurate, your SI extraction is correct. When your design goes to manufacturing, it must work!

Let’s get started!

Mirror versus Mirror Geometry
First things first. Just what are the types of mirroring supported in the package layout tools?

• Not Mirrored – This is your default state. The object exists exactly as it was defined.
  • For an IC, this would be chip-up orientation, with the pins facing up (if sitting on/above the top substrate layer, this means they face AWAY from the substrate). Remember that in almost all IC designs, the top metal layer is the highest in the layer ordering. M1 is down in the core of the IC.
  • With a discrete component like a resistor, this would be positioned sitting on top of the top package substrate layer with the body above.
  • Applied to vias, this is oriented relative to the top substrate layer and drilling down.
• Mirrored Geometry – This is a mirroring through the Y-axis only.
  • For an IC, this represents the chip-down orientation. Mounted to the top substrate layer, this is the normal orientation for a flip-chip, chip-down die. If you are mounting a wire-bond die component to be slot bonded through to bond fingers on the bottom substrate layer, this is also chip-down / mirrored geometry. The mirror geometry orientation for a die component inverts the die component without changing its package interface pins’ layers.
  • With a discrete component, mirror geometry is only used when placed in an embedded status. This would be equivalent to mounting the resistor with its pins sticking up. If the pins are on the top substrate layer, then its body sunk into the package substrate itself.
  • Applied to a via or via structure, this leaves the start and end layers for the drilling action unchanged but reverses the geometry of the pads (and the drill hole pattern if it’s multi-drill). The best example would be an unlikely pad shaped like a left-pointing arrow. In mirror geometry orientation, it would point to the right.
• Mirrored – This is a geometry mirror through the Y-axis PLUS a mirroring of the layers. A pad that used to be on top will now be on bottom.
  • For an IC, this mirror status is never used. To mount a die on the bottom of the package, you would use the die stack editor and set its front pin layer to be bottom and its orientation to be chip-up (not mirrored). Because the IC design is done with the pins on the top, this puts the solder bumps on the correct side.
  • Mirrored is never used for dies because die stack layers are outside the substrate. There is no corresponding layer to specifically mirror to.
  • With a discrete component, this indicates a mounting change from the default top mount to a bottom mount. This only applies for surface mounting, however. If you are placing a component on an embedded layer, mirror geometry is used in combination with the embedded layer and the layer’s body up / body down definition.
  • Applied to a via, this changed the drill side from the top to the bottom. If this were a bb via with a definition going from layer 2 to 3 in a 10-layer stack-up, mirrored the drill goes from layer 9-8. The pad geometry from layer 2 is on layer 9, layer 3 maps to layer 8.

For perspective, the following shows a (very contrived) padstack with pads on top and bottom in the different orientations. You can see that only the mirrored option changes the layer mappings for the two pads, and how its arrow “points” the same direction as the non-layer changing mirror geometry.

Why the difference?
Why do different components work differently, you might ask? Why does an IC not follow the same rules as a discrete component? And that’s a very good, important question. It primarily stems from two sources.

One of those is the ease of use – it is typically much easier for a designer to look at the component on the substrate and then the padstack definitions in the padstack editor tool and see consistency in the layer name mappings.

The other comes from the mounting styles. Die components are often stacked – whether it is a large stack of memory dies with a controller on the top, an interposer with multiple flip-chip dies positioned side-by-side, or even a flip-chip in a cavity with a wire-bond die mounted on top of it.

A die’s physical symbol should always be defined in its chip-up orientation. Whether you are creating a DRA symbol manually as a librarian, reading the pin locations in from a symbol spreadsheet or die text file, or receiving a co-design XDA file from the IC designer on the project, the orientation needs to be consistent. The LAST thing you want to do is to create your wire-bond die definitions in chip-up orientation and your flip-chips in chip-down. You will, inevitably, forget at some point and the results can be disastrous. Keeping things simple is (at least for me!) the best practice. Don’t forget, either, that some dies can be used in both wire-bond AND flip-chip configurations with the same IC design – as in the simplified example below, which has the same die placed both WB and FC. You don’t want to create and manage two library elements for the same die, either.

Discrete components, on the other hand, are nearly always off-the-shelf elements sourced from someone else. They will often be defined the same for both a traditional PCB and an IC package design, even. Again, consistency of definition (in this case, they are all “body up” for mounting on the top layer by default) rules the day.

Checking you’re right
You’ll likely want to verify things before you send your design for SI analysis, and certainly before you go to manufacturing and assembly. It’s possible you’ll even want to run a formal LVS check with a sign-off tool. All of these require all components to be in the proper orientations.

A quick first check you can do right in the main layout editor is with the die stack editor. Bringing this up will show you a graphical rendering of the relationship and mount orientations of all the components, plus a table listing. If anything is incorrect, you can fix them with a click of the mouse here. Should you want, there’s even a button to view just this stack in the 3D Viewer where you can pan, zoom, rotate, and measure things.

Once you’ve verified the die stacks themselves, it’s a good idea to bring the entire layout into the 3D tool. This will show you the relationships between objects, how the dies stack up (pun intended) next to the substrate layer thicknesses when placed in a cavity, or how high bond wires rise above the substrate surface for calculating molding cap dimensions or minimum BGA ball heights.

Summary
The largest take-away from this, I hope, is that you should always make sure your die symbol definitions are in the chip-up orientation to allow you to use them as both wire-bond and flip-chip mounting styles, but also to make sure if you communicate with your IC designer, you’re using a consistent view of the design.

Dies are always placed using the mirror geometry option, which corresponds to the chip-down mounting style. The layer the die sits on is driven through the die stack editor, as is the back-side pin layer for your two-sided components.

Off-the-shelf components like resistors and capacitors, which share their use across both package and PCB layouts and are typically designed for mounting only on the top or bottom substrate layers, use the front-to-back mirror option.

Lastly, vias, via structures, and even bond fingers use mirror geometry so that they can be used on both the left and right sides of the escape routing to achieve identical patterns.