Design For Silicon Success At 7nm

Rising complexity and tighter design margins increase the cost, and likelihood, of design failure.


Next-generation automotive, mobile and high-performance computing applications demand the use of 7nm SoCs to deliver greater functionality and higher performance at much lower power. According to Gartner, when compared to 16nm/14nm technology, 7nm offers 35% speed improvement, 65% less power, and 3.3X density improvement. Hence, despite a whopping cost of $271M — per Gartner’s estimate — to design a 7nm chip, SoC design houses that can leverage economies of scale are continuing to adopt this technology to remain competitive. With aggressive time-to-market requirements, all that investment is wasted if the silicon fails, or even if it is late to market. Simply put, the cost of design failure is huge.

Increased Design Complexity
7nm SoCs are faster, bigger, yet more complex, with a great deal of high-speed I/Os, analog, mixed signal and RF IPs integrated on the same substrate next to fast switching, low power digital logic. Along with thinner wires, the increased device density leads to longer wires, and hence greater routing congestion. The devices, driving higher currents with faster slew rates into those wires, pose significant challenges to both power and timing closure.

Tighter Design Margins
Sub-500mV operating voltages lead to tighter noise margins, resulting in a chip that is very sensitive to changes in supply voltage. For instance, a 100mV noise in 1V supply at 28nm technology constituted only 10% of the operating voltage. The same drop at sub-500mV supply will translate to 25% to 30% of the nominal supply, rendering a device anywhere from non-functional to causing timing and clock failures that are catastrophic. The real challenge, given the size of such designs, is how to zero in on the must-fix violations?

The heat trapped in the 3D fin structures of finFET devices lead to significant on-chip temperature variations and self-heating. In addition, the high current density causes localized joule heating of the wires. This on-chip temperature variation is further exacerbated by power gating and clock gating logic used to turn off the unused parts of a chip and clocks signals. With such a wide variation of temperature, a constant high temperature based EM methodology flags a lot of false EM violations, which takes time and effort to fix. In essence, higher temperature, higher resistance and higher current lead to significant on-chip EM issues, requiring a thermal-aware EM methodology to ensure silicon success.

Margin Driven Analysis Leads to Overdesign
To simplify the design process, traditionally designers have solved each design attribute individually — in silo — with a worst-case and best-case assumption of the other. For example, EM sign-off is done at a constant temperature across the chip, while timing sign-off is done assuming a worst-case voltage drop. Such margin-based approaches lead to overdesign. Especially with routing being severely constrained, it becomes a very expensive proposition. This silo based approach leads to overdesign and results in larger, more expensive chips with lower than expected performance. Overdesign also consumes more resources and time for achieving design convergence with no guarantee of product success.

Increased Demand for Design Coverage
To add to these woes, there are hundreds of combinations of PVT corners to solve because the number of cores on an SoC has increased, and so has the number of applications. For example, an ADAS SoC is used for a variety of applications such as pedestrian detection, parking assist, vehicle exit assist, night vision, blind spot monitoring, collision avoidance, and a whole lot more. The numbers of vectors for which you need to run simulations have increased multi-fold. It is nearly impossible to uncover potential design weaknesses when you are simulating a handful of vectors for just a fraction of second. How do you ensure you have enough design coverage?

Increased Demand for Scalability and Performance
As the design size increases, the turnaround time for solving 1 billion-plus instance designs becomes very critical. The solution should scale elastically with capacity and performance. It is imperative to iterate designs over multiple operating conditions and scenarios rapidly, with an overnight turnaround time to maximize design coverage. Also, it is equally important to gain key insights from these large design databases to prioritize design fixes.

Need for Chip-Package-System Co-Optimization
Advanced SoCs also mandate the use of advanced packaging technologies like 2.5/3D or wafer-level packaging. These technologies have blurred the boundaries between a chip and package. Existing margin-driven approaches of separately designing a chip, package and board severely limits the ability to globally optimize these systems without over-designing. The choice of packaging, metallization stack, the amount of decaps on-chip and off-chip all translate to cost. Economics of sub-10nm technology requires the judicious use of routing resources. Hence a holistic approach to solve the PDN network that is operating across different frequency domains of the chip, package and board is mandatory to optimize the available resources across the spectrum. A system-aware chip analysis and a chip-aware system analysis that can address power, signal, thermal integrity along with EMI and EMC is critical.

Power grid design cannot be an afterthought, it has to be considered up front and optimized in-design. In-design analysis is critical to detect grid weakness issues, optimize sensitive RF/analog block placement and understand power/thermal profile as the design evolves to meet the desired performance goals of the chip, package and system as a whole.

Steps to successful power noise reliability sign-off

Check out the ANSYS webinar on design methodologies to address finFET challenges related to power integrity and its impact on timing, thermal issues and reliability.

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